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1. 发明授权

US09257184B2 Nonvolatile memory systems with embedded fast read and write memories 有权
公开(公告)号：US09257184B2
公开(公告)日：2016-02-09
申请号：US14335160
申请日：2014-07-18
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C14/00 , G11C16/06 , G11C7/00 , G11C16/10 , G11C7/10 , G11C11/02 , G11C11/22 , G11C13/00
CPC分类号： G06F12/10 , G06F2212/205 , G06F2212/214 , G11C7/1006 , G11C7/1084 , G11C11/02 , G11C11/225 , G11C13/0021 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C16/10
摘要： A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

2. 发明授权

US09190502B2 Semiconductor devices with graded dopant regions 有权
标题翻译：具有渐变掺杂区域的半导体器件
公开(公告)号：US09190502B2
公开(公告)日：2015-11-17
申请号：US14515584
申请日：2014-10-16
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： H01L21/02 , H01L29/739 , H01L27/115 , H01L29/36 , H01L27/02 , H01L27/108
CPC分类号： H01L29/1095 , H01L27/0214 , H01L27/10844 , H01L27/11521 , H01L27/11524 , H01L27/14643 , H01L29/36 , H01L29/7395
摘要： Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.
摘要翻译：目前制造的大多数半导体器件在侧向或垂直器件的有源（和隔离）区域中具有均匀的掺杂剂浓度。通过对掺杂剂浓度进行分级，可以显着改善各种半导体器件中的性能。在诸如数字逻辑，各种功率MOSFET和IGBT ICS的操作频率的增加，DRAM的刷新时间的改善，非易失性存储器的编程时间的减少，包括像素分辨率和颜色灵敏度的更好的视觉质量的应用特定领域中可以获得性能改进用于成像IC，可变滤波器中变容二极管的灵敏度更高，JFET的更高驱动能力以及许多其他应用。

3. 发明授权

US07855916B2 Nonvolatile memory systems with embedded fast read and write memories 有权
标题翻译：具有嵌入式快速读写存储器的非易失性存储器系统
公开(公告)号：US07855916B2
公开(公告)日：2010-12-21
申请号：US12256362
申请日：2008-10-22
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C11/34 , G11C16/04 , G06F9/26
CPC分类号： G06F12/10 , G06F2212/205 , G06F2212/214 , G11C7/1006 , G11C7/1084 , G11C11/02 , G11C11/225 , G11C13/0021 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C16/10
摘要： A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.
摘要翻译：使用具有随机存取易失性存储器的非易失性存储存储器的新颖结构来描述非易失性存储器包括新的命令以增强内存系统的读写性能。

4. 发明授权

US07787311B2 Memory with programmable address strides for accessing and precharging during the same access cycle 有权
标题翻译：具有可编程地址步长的存储器，用于在相同的访问周期内访问和预充电
公开(公告)号：US07787311B2
公开(公告)日：2010-08-31
申请号：US11937407
申请日：2007-11-08
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C8/18
CPC分类号： G06F12/0215 , G06F12/0607 , G11C7/1042 , G11C7/12 , G11C11/4082 , G11C11/4094
摘要： Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells.
摘要翻译：本公开的实施例提供方法，装置和系统，其包括被配置为存储和输出多个不同大小的多个地址步幅的存储器，以使得能够访问和预充电电路至少部分地基于第一和第二组存储器单元访问和预充电所述多个地址在所述主机装置/系统的操作期间跨步，所述第一和第二组存储器单元是不同的存储单元组。

5. 发明申请

US20100202230A1 MEMORIES WITH FRONT END PRECHARGE 有权
标题翻译：具有前端预备的记忆
公开(公告)号：US20100202230A1
公开(公告)日：2010-08-12
申请号：US12767517
申请日：2010-04-26
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/12 , G11C11/405 , G11C11/4076 , G11C11/4094
摘要： Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells.
摘要翻译：操作数字存储器的方法，装置和系统，其中包括多个存储器单元的数字存储器件接收对一组存储器单元执行操作的命令，其中该组存储器单元包含比该器件作为整体更少的存储器单元并且其中所述设备执行所述操作，包括响应于所接收的命令，仅选择性地对所述操作的前端进行预充电，仅与所述存储器单元组相关联的一组位线。

6. 发明授权

US07724593B2 Memories with front end precharge 有权
标题翻译：记忆与前端预充电
公开(公告)号：US07724593B2
公开(公告)日：2010-05-25
申请号：US11771853
申请日：2007-06-29
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/12 , G11C11/405 , G11C11/4076 , G11C11/4094
摘要： Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells.
摘要翻译：操作数字存储器的方法，装置和系统，其中包括多个存储器单元的数字存储器件接收对一组存储器单元执行操作的命令，其中该组存储器单元包含比该器件作为整体更少的存储器单元并且其中所述设备执行所述操作，包括响应于所接收的命令，仅选择性地对所述操作的前端进行预充电，仅与所述存储器单元组相关联的一组位线。

7. 发明申请

US20100006138A1 SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS 有权
标题翻译：具有分级垄断区域的半导体器件
公开(公告)号：US20100006138A1
公开(公告)日：2010-01-14
申请号：US12549283
申请日：2009-08-27
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： H01L31/042 , H01L27/092
CPC分类号： H01L29/7395 , H01L21/823878 , H01L21/823892 , H01L27/0214 , H01L27/10844 , H01L27/11521 , H01L27/11524 , H01L27/14643 , H01L31/02021 , H02S40/32 , Y02E10/50
摘要： Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.
摘要翻译：目前制造的大多数半导体器件在侧向或垂直器件的有源（和隔离）区域中具有均匀的掺杂剂浓度。通过对掺杂剂浓度进行分级，可以显着改善各种半导体器件中的性能。在诸如数字逻辑，各种功率MOSFET和IGBT ICS的操作频率的增加，DRAM的刷新时间的改善，非易失性存储器的编程时间的减少，包括像素分辨率和颜色灵敏度的更好的视觉质量的应用特定领域中可以获得性能改进用于成像IC，可变滤波器中变容二极管的灵敏度更高，JFET的更高驱动能力以及许多其他应用。

8. 发明申请

US20090237997A1 RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT 有权
标题翻译：具有CMOS兼容非易失性存储元件的随机存取存储器
公开(公告)号：US20090237997A1
公开(公告)日：2009-09-24
申请号：US12053976
申请日：2008-03-24
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0433 , G11C11/56 , G11C13/0004 , G11C14/00 , G11C14/0018 , G11C14/0036 , G11C14/0045 , G11C2213/79
摘要： Embodiments provide systems, methods, and apparatuses with a plurality of row lines and column lines arranged in a matrix, and at least one memory cell having an access transistor and a CMOS-compatible non-volatile storage element coupled to the access transistor in series. The CMOS-compatible non-volatile storage element includes a node and is configured to hold a charge corresponding to a n-bit binary value where n is an integer greater than 1. The access transistor has a word line gate coupled to a row line, a first node coupled to a column line, a second node coupled to a storage node, with the storage node connected to said node of the CMOS-compatible non-volatile storage element. Access circuitry coupled to the memory cell is configured to activate the memory cell and sense a resulting current corresponding to the n-bit binary value.
摘要翻译：实施例提供具有以矩阵形式布置的多条行线和列线的系统，方法和装置，以及至少一个存储单元，其具有与串联存取晶体管的存取晶体管和CMOS兼容的非易失性存储元件。 CMOS兼容的非易失性存储元件包括一个节点，并被配置为保持与n位二进制值对应的电荷，其中n是大于1的整数。存取晶体管具有耦合到行线的字线栅极，耦合到列线的第一节点，耦合到存储节点的第二节点，所述存储节点连接到所述CMOS兼容的非易失性存储元件的所述节点。耦合到存储器单元的访问电路被配置为激活存储器单元并感测对应于n位二进制值的结果电流。

9. 发明申请

US20090106505A1 DIGITAL MEMORY WITH FINE GRAIN WRITE OPERATION 有权
标题翻译：具有精细格式写入操作的数字存储器
公开(公告)号：US20090106505A1
公开(公告)日：2009-04-23
申请号：US11875636
申请日：2007-10-19
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G06F12/00
CPC分类号： G06F11/1044 , G11C2029/0411
摘要： Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction.
摘要翻译：用于操作数字存储器的方法，系统和装置，包括由控制器确定要写入数字存储器的位并由控制器写入该位。该位可以是包括多个位的数据字的一部分，并且可以以比数据字更精细的粒度级执行确定和写入。在实施例中，要写入的位可以通过纠错来确定。

10. 发明授权

US5963468A Low latency memories and systems using the same 失效
标题翻译：低延迟存储器和使用它的系统
公开(公告)号：US5963468A
公开(公告)日：1999-10-05
申请号：US016559
申请日：1998-01-30
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C7/18 , G11C8/12 , G11C8/16 , G11C11/405 , G11C11/406 , G11C11/4097 , G11C11/24
CPC分类号： G11C7/18 , G11C11/405 , G11C11/406 , G11C11/4097 , G11C8/12 , G11C8/16
摘要： A memory 400 including a memory cell 501 disposed at the intersection of an addressable row and addressable column, memory cell 501 being accessible via a selected one of a pair of wordlines 503a, 503b associated with the row and a selected one of a pair of bitlines 502a, 502b associated with the column.
摘要翻译：存储器400，其包括设置在可寻址行和可寻址列的交叉点处的存储器单元501，存储器单元501可通过与行相关联的一对字线503a，503b中的所选择的一个和一对位线 502a，502b。

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