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1. 发明申请

US20070057735A1 Voltage-controlled oscillator for low-voltage, wide frequency range operation 有权
公开(公告)号：US20070057735A1
公开(公告)日：2007-03-15
申请号：US11224256
申请日：2005-09-12
申请人： Vincent von Kaenel
发明人： Vincent von Kaenel
IPC分类号： H03L7/00
CPC分类号： H03L7/0996 , H03L7/0891 , H03L7/093 , H03L7/18
摘要： In one embodiment, an apparatus comprises a voltage-controlled oscillator (VCO) that comprises a circuit coupled to receive an input control voltage to the VCO and configured to generate a second voltage responsive to the input control voltage, a summator coupled to receive the input control voltage and the second voltage, and an oscillator coupled to receive the output voltage of the summator. The summator is configured to combine the input control voltage and the second voltage to generate the output voltage. The oscillator is configured to oscillate an output signal, wherein a frequency of oscillation of the output signal is controlled by the output voltage of the summator.

2. 发明授权

US06104251A Method and apparatus for providing transient suppression in a central processor unit (CPU) phase locked loop clock (PLL) clock signal synthesis circuit 有权
标题翻译：在中央处理器单元（CPU）锁相环（PLL）时钟信号合成电路中提供瞬态抑制的方法和装置
公开(公告)号：US06104251A
公开(公告)日：2000-08-15
申请号：US143945
申请日：1998-08-31
申请人： Delvan A. Ramey , Vincent von Kaenel
发明人： Delvan A. Ramey , Vincent von Kaenel
IPC分类号： G06F1/08 , H03L7/089 , H03L7/14 , H03L7/199 , H03L7/085 , H03L7/18
CPC分类号： H03L7/199 , G06F1/08 , H03L7/0893 , H03L7/0896 , H03L7/14
摘要： The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.
摘要翻译：本发明涉及用于减少中央处理单元的锁相环（PLL）电路中的瞬态信号的装置和方法。本发明的一个方面涉及一种方法和装置，当PLL电路的输出信号的频率变化被实现以限制PLL产生的瞬态信号时，禁用锁相环电路中的电荷泵电路。本发明的另一方面涉及一种用于协调CPU的PLL中的分频器的分频值的变化以限制来自PLL的瞬态信号的方法和装置。

3. 发明申请

US20070002636A1 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US20070002636A1
公开(公告)日：2007-01-04
申请号：US11173565
申请日：2005-07-01
申请人： Brian Campbell , Vincent von Kaenel , Daniel Murray , Gregory Scott , Sribalan Santhanam
发明人： Brian Campbell , Vincent von Kaenel , Daniel Murray , Gregory Scott , Sribalan Santhanam
IPC分类号： G11C7/10
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

4. 发明授权

US07038487B2 Multi-function interface 有权
标题翻译：多功能接口
公开(公告)号：US07038487B2
公开(公告)日：2006-05-02
申请号：US10944304
申请日：2004-09-17
申请人： Joseph Ingino , Vincent Von Kaenel
发明人： Joseph Ingino , Vincent Von Kaenel
IPC分类号： H03K19/003
CPC分类号： H03K19/018557 , H04L25/028
摘要： A multi-function interface includes a digital interface module and a configurable output impedance module. The digital interface module is operably coupled to pass a first type of input signal when the multi-function interface is in a first mode and operably coupled to pass a second type of input signal when the multi-function interface is in a second mode. The configurable output impedance module is operably coupled to the digital interface to provide a first output impedance when the multi-function interface is in the first mode and to provide a second output impedance when the multi-function interface is in the second mode.
摘要翻译：多功能接口包括数字接口模块和可配置的输出阻抗模块。当多功能接口处于第一模式时，数字接口模块可操作地耦合以通过第一类型的输入信号，并且当多功能接口处于第二模式时可操作地耦合以传递第二类型的输入信号。当多功能接口处于第一模式时，可配置输出阻抗模块可操作地耦合到数字接口以提供第一输出阻抗，并且当多功能接口处于第二模式时提供第二输出阻抗。

5. 发明授权

US5682118A Circuit for controlling the voltages between well and sources of the transistors of and MOS logic circuit, and system for slaving the power supply to the latter including the application thereof 失效
标题翻译：用于控制MOS逻辑电路的晶体管的阱和源极之间的电压的电路以及向后者供电的系统包括其应用
公开(公告)号：US5682118A
公开(公告)日：1997-10-28
申请号：US409712
申请日：1995-03-24
申请人： Vincent Von Kaenel , Matthijs Daniel Pardoen
发明人： Vincent Von Kaenel , Matthijs Daniel Pardoen
IPC分类号： H01L27/04 , G05F3/24 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K19/0944 , H03K3/01
CPC分类号： G05F3/24
摘要： The control circuit includes a reference MOS transistor (24) on which preermined operating characteristics are imposed. Circuitry (21, 22, 23) is provided for comparing an operating characteristic of the transistor (24) with a reference value (V.sub.tnref) so as to produce a control voltage. This voltage, after adaptation, is applied to the transistor (24) so as to fix the threshold voltage (V.sub.th) thereof, in such a way as to maintain the operating characteristics of the transistor (24). This same threshold voltage is then imposed on all the transistors of the logic circuit with which the control circuit is associated. This control circuit makes it possible particularly to reduce the consumption of said logic circuit.
摘要翻译：控制电路包括其上施加预定操作特性的参考MOS晶体管（24）。提供电路（21,22,23），用于将晶体管（24）的工作特性与基准值（Vtnref）进行比较，以产生控制电压。在适应之后，将该电压施加到晶体管（24）以固定其阈值电压（Vth），以保持晶体管（24）的工作特性。然后将相同的阈值电压施加在与控制电路相关联的逻辑电路的所有晶体管上。该控制电路特别能够降低所述逻辑电路的消耗。

6. 发明申请

US20050030061A1 Multi-function interface 有权
标题翻译：多功能接口
公开(公告)号：US20050030061A1
公开(公告)日：2005-02-10
申请号：US10944304
申请日：2004-09-17
申请人： Joseph Ingino , Vincent Von Kaenel
发明人： Joseph Ingino , Vincent Von Kaenel
IPC分类号： H03K19/003
CPC分类号： H03K19/018557 , H04L25/028
摘要： A multi-function interface includes a digital interface module and a configurable output impedance module. The digital interface module is operably coupled to pass a first type of input signal when the multi-function interface is in a first mode and operably coupled to pass a second type of input signal when the multi-function interface is in a second mode. The configurable output impedance module is operably coupled to the digital interface to provide a first output impedance when the multi-function interface is in the first mode and to provide a second output impedance when the multi-function interface is in the second mode.
摘要翻译：多功能接口包括数字接口模块和可配置的输出阻抗模块。当多功能接口处于第一模式时，数字接口模块可操作地耦合以通过第一类型的输入信号，并且当多功能接口处于第二模式时可操作地耦合以传递第二类型的输入信号。当多功能接口处于第一模式时，可配置输出阻抗模块可操作地耦合到数字接口以提供第一输出阻抗，并且当多功能接口处于第二模式时提供第二输出阻抗。

7. 发明申请

US20070229054A1 Operating an Integrated Circuit at a Minimum Supply Voltage 有权
标题翻译：以最小电源电压操作集成电路
公开(公告)号：US20070229054A1
公开(公告)日：2007-10-04
申请号：US11753853
申请日：2007-05-25
申请人： Daniel Dobberpuhl , Vincent von Kaenel
发明人： Daniel Dobberpuhl , Vincent von Kaenel
IPC分类号： G01R31/28
CPC分类号： G06F1/3203 , G01R31/2879 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.
摘要翻译：在一个实施例中，集成电路包括至少一个测量单元，其被配置为产生指示集成电路可用于给定工作频率的电源电压的输出，以及耦合以接收输出的控制单元。控制单元被配置为响应于输出而产生指示集成电路的所请求的电源电压的电压控制输出。电压控制输出可以从集成电路输出供集成电路外部的电路使用，以便为集成电路产生电源电压。

8. 发明申请

US20070001747A1 Rapid supply voltage ramp 有权
标题翻译：快速电源电压斜坡
公开(公告)号：US20070001747A1
公开(公告)日：2007-01-04
申请号：US11173582
申请日：2005-07-01
申请人： Vincent von Kaenel
发明人： Vincent von Kaenel
IPC分类号： G05F1/10
CPC分类号： G06F1/26 , H02J7/345 , Y10S323/901
摘要： In one embodiment, an apparatus is provided for a system including an integrated circuit coupled to a node to receive a supply voltage and having bypass capacitors coupled in parallel with the integrated circuit to the node. The apparatus comprises a first capacitor, a switch coupled to the first capacitor, and a voltage source configured to charge the first capacitor. The switch is coupled to receive a control signal that is asserted, during use, if the supply voltage to an integrated circuit is to be increased. The switch is configured to electrically couple the first capacitor to the node in response to an assertion of the control signal. When electrically coupled to the node, the first capacitor supplies charge to the bypass capacitors. A system comprising the apparatus, the node, the integrated circuit, and the bypass capacitors is also contemplated in some embodiments.
摘要翻译：在一个实施例中，提供了一种用于系统的装置，该系统包括耦合到节点的集成电路以接收电源电压并且具有与集成电路并联耦合到节点的旁路电容器。该装置包括第一电容器，耦合到第一电容器的开关和被配置为对第一电容器充电的电压源。该开关被耦合以接收在使用期间如果要增加集成电路的电源电压而被断言的控制信号。开关被配置为响应于控制信号的断言将第一电容器电耦合到节点。当电耦合到节点时，第一电容器向旁路电容器提供电荷。在一些实施例中也可以考虑包括该装置，节点，集成电路和旁路电容器的系统。

9. 发明申请

US20050218957A1 Programmable frequency multiplier 审中-公开
标题翻译：可编程倍频器
公开(公告)号：US20050218957A1
公开(公告)日：2005-10-06
申请号：US11146566
申请日：2005-06-07
申请人： Haluk Konuk , Vincent von Kaenel , Dai Le
发明人： Haluk Konuk , Vincent von Kaenel , Dai Le
IPC分类号： G06F1/06 , H03B19/00 , H03K3/03 , H03K3/70 , H03K5/01
CPC分类号： H03K3/70 , H03K3/0315
摘要： In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.
摘要翻译：在一个实施例中，时钟倍增器电路被耦合以接收输入信号，并被配置为产生输出时钟信号。时钟倍增器电路被配置为响应于输入信号的边沿而在输出时钟信号上产生多个脉冲，其中脉冲具有与产生的脉冲数无关的宽度，并且独立于输入信号的频率。脉冲数可以选择。在另一个实施例中，时钟倍增器电路包括电路和振荡器。电路被配置为响应于控制信号而在时钟乘法器电路的输出时钟信号上产生多个脉冲。振荡器被配置为产生具有宽度的流脉冲，其中电路被耦合以接收脉冲流。

10. 发明授权

US06809547B2 Multi-function interface and applications thereof 有权
标题翻译：多功能接口及其应用
公开(公告)号：US06809547B2
公开(公告)日：2004-10-26
申请号：US10305648
申请日：2002-11-27
申请人： Joseph Ingino , Vincent Von Kaenel
发明人： Joseph Ingino , Vincent Von Kaenel
IPC分类号： H03K19003
CPC分类号： H03K19/018571 , G06F13/4072 , H04L25/0278 , H04L25/028
摘要： A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1st type of input signal when the interface is in a 1st mode and operably coupled to pass a 2nd type of input signal when the interface is in a 2nd mode. The configurable driver module is operably coupled to amplify the 1st type of input signal when the interface is in the 1st mode and to amplify the 2nd type of input signal when the interface is in the 2nd mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1st output impedance of the interface when the interface is in the 1st mode and to provide a 2nd output impedance when the interface is in the 2nd mode.

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