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1. 发明申请

US20060139109A1 PLL-based frequency synthesizer 审中-公开
标题翻译：基于PLL的频率合成器
公开(公告)号：US20060139109A1
公开(公告)日：2006-06-29
申请号：US11235787
申请日：2005-09-27
申请人： Alain Oustaloup , Yann Deval , Didier Belot , Pierre Melchior , Jean-Baptiste Begueret , Franck Badets , Vincent Lagareste
发明人： Alain Oustaloup , Yann Deval , Didier Belot , Pierre Melchior , Jean-Baptiste Begueret , Franck Badets , Vincent Lagareste
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03H7/06 , H03L7/0891 , H03L7/18
摘要： The frequency synthesizer includes a phase-locked loop (PLL). The PLL includes an oscillator controlled to deliver an output signal at a predefined output frequency, a variable frequency divider to convert the output signal into a divided-frequency signal, a phase comparator to produce a signal measuring a phase difference between the divided-frequency signal and a reference signal at a reference frequency, and a loop filter to control the oscillator on the basis of the measurement signal. To increase the speed of convergence of the synthesizer if the set point is changed, the loop filter of the PLL is a fractional, i.e. non-integer, order low-pass filter.
摘要翻译：频率合成器包括锁相环（PLL）。 PLL包括被控制以以预定的输出频率传送输出信号的振荡器，用于将输出信号转换成分频信号的可变分频器，相位比较器，以产生测量分频信号之间的相位差的信号以及参考频率的参考信号，以及环路滤波器，用于根据测量信号控制振荡器。为了增加合成器的收敛速度，如果设定点改变，PLL的环路滤波器是分数即非整数阶低通滤波器。

2. 发明授权

US07315214B2 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US07315214B2
公开(公告)日：2008-01-01
申请号：US11400062
申请日：2006-04-07
申请人： Franck Badets , Didier Belot , Vincent Lagareste , Yann Deval , Pierre Melchior , Jean-Baptiste Begueret
发明人： Franck Badets , Didier Belot , Vincent Lagareste , Yann Deval , Pierre Melchior , Jean-Baptiste Begueret
IPC分类号： H03L7/00 , H03L7/07 , H03L7/087
CPC分类号： H03L7/093 , H03L7/087 , H03L7/0893 , H03L7/18 , H03L2207/06
摘要： A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.
摘要翻译：锁相环包括用于以确定的输出频率输出输出信号的受控振荡器和用于将输出信号转换为分频的信号的可变分频器。 PLL被称为复合，因为它包括至少一个具有环路滤波器的第一环路，该环路滤波器基于分频频率的信号产生用于振荡器的第一控制信号，以及具有不同于环路的环路滤波器的第二环路滤波器，用于基于分频后的信号产生用于对振荡器进行附加控制的第二信号。第一回路的环路滤波器和第二回路的环路滤波器具有不同的各自的截止频率。第一个环路的通带可以适应于确保PLL的收敛和稳定性，而第二个环路可以提供额外的通带，在修改输出预置值的情况下可以提高PLL的自适应速度频率。

3. 发明申请

US20060232344A1 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US20060232344A1
公开(公告)日：2006-10-19
申请号：US11400062
申请日：2006-04-07
申请人： Franck Badets , Didier Belot , Vincent Lagareste , Yann Deval , Pierre Melchior , Jean-Baptiste Begueret
发明人： Franck Badets , Didier Belot , Vincent Lagareste , Yann Deval , Pierre Melchior , Jean-Baptiste Begueret
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03L7/087 , H03L7/0893 , H03L7/18 , H03L2207/06
摘要： A phase locked loop includes a controlled oscillator for delivering an output signal at a determined output frequency, and a variable frequency divider for converting the output signal into a signal at divided frequency. The PLL is termed composite in that it includes at least one first loop having a loop filter for generating a first control signal for the oscillator on the basis of the signal at divided frequency, and a second loop having a loop filter, different from the loop filter of the first loop, for generating, on the basis of the signal at divided frequency, a second signal for additional control of the oscillator. The loop filter of the first loop and the loop filter of the second loop have different respective cutoff frequencies. The passband of the first loop, can be adapted to ensure the convergence and the stability of the PLL, while the second loop can afford extra passband increasing the speed of adaptation of the PLL in case of modification of the value of a preset for the output frequency.
摘要翻译：锁相环包括用于以确定的输出频率输出输出信号的受控振荡器和用于将输出信号转换为分频的信号的可变分频器。 PLL被称为复合，因为它包括至少一个具有环路滤波器的第一环路，该环路滤波器基于分频频率的信号产生用于振荡器的第一控制信号，以及具有不同于环路的环路滤波器的第二环路滤波器，用于基于分频后的信号产生用于对振荡器进行附加控制的第二信号。第一回路的环路滤波器和第二回路的环路滤波器具有不同的各自的截止频率。第一个环路的通带可以适应于确保PLL的收敛和稳定性，而第二个环路可以提供额外的通带，在修改输出预置值的情况下可以提高PLL的自适应速度频率。

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