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1. 发明授权

US07398595B2 Method for forming a storage cell capacitor compatible with high dielectric constant materials 有权
标题翻译：用于形成与高介电常数材料兼容的存储单元电容器的方法
公开(公告)号：US07398595B2
公开(公告)日：2008-07-15
申请号：US11458072
申请日：2006-07-17
申请人： Pierre C. Fazan , Viju K. Mathews
发明人： Pierre C. Fazan , Viju K. Mathews
IPC分类号： H01K3/10
CPC分类号： H01L27/11502 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L27/11507 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , H01L28/91 , Y10T29/435 , Y10T29/49165
摘要： An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
摘要翻译：集成电路结构包括数字线和适于作为存储单元电容器的一部分的电极，并且包括介于导电插塞和抗氧化层之间的阻挡层。绝缘层在电介质层的沉积和退火期间保护阻挡层的侧壁。该方法包括形成凹入绝缘层中的导电插塞。阻挡层形成在凹部和顶层中。在凹部中形成抗氧化导电层和另外的氧化物层。将导电层平坦化以暴露氧化物或氧化物/氮化物层。然后蚀刻氧化物层以暴露导电层的顶表面和垂直部分。形成介电层以覆盖存储节点电极。制造电池板电极以覆盖电介质层。

2. 发明授权

US07385240B2 Storage cell capacitor compatible with high dielectric constant materials 有权
标题翻译：存储单元电容与高介电常数材料兼容
公开(公告)号：US07385240B2
公开(公告)日：2008-06-10
申请号：US11276639
申请日：2006-03-08
申请人： Pierre C. Fazan , Viju K. Mathews
发明人： Pierre C. Fazan , Viju K. Mathews
IPC分类号： H01L27/108
CPC分类号： H01L27/11502 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L27/11507 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , H01L28/91 , Y10T29/435 , Y10T29/49165
摘要： An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
摘要翻译：集成电路结构包括数字线和适于作为存储单元电容器的一部分的电极，并且包括介于导电插塞和抗氧化层之间的阻挡层。绝缘层在电介质层的沉积和退火期间保护阻挡层的侧壁。该方法包括形成凹入绝缘层中的导电插塞。阻挡层形成在凹部和顶层中。在凹部中形成抗氧化导电层和另外的氧化物层。将导电层平坦化以暴露氧化物或氧化物/氮化物层。然后蚀刻氧化物层以暴露导电层的顶表面和垂直部分。形成介电层以覆盖存储节点电极。制造电池板电极以覆盖电介质层。

3. 发明授权

US06835634B1 Streamlined field isolation process 失效
标题翻译：流线型现场隔离流程
公开(公告)号：US06835634B1
公开(公告)日：2004-12-28
申请号：US09037945
申请日：1998-03-10
申请人： Pierre C. Fazan , Viju K. Mathews , Nanseng Jeng
发明人： Pierre C. Fazan , Viju K. Mathews , Nanseng Jeng
IPC分类号： H01L21762
CPC分类号： H01L21/76202
摘要： A field isolation process performed on a silicon wafer is carried out by high pressure oxidation. Using oxygen rather than water vapor as the oxidant substantially eliminates nitride inclusions via the Kooi effect. Preferred high pressure field oxidation processes simplify all CMOS flows by eliminating the need for sacrificial oxide growth and removal steps.
摘要翻译：通过高压氧化进行在硅晶片上进行的场隔离处理。使用氧气而不是水蒸气作为氧化剂，基本上消除了通过Kooi效应的氮化物夹杂物。优选的高压场氧化工艺通过消除对牺牲氧化物生长和去除步骤的需要来简化所有CMOS流程。

4. 发明授权

US5445999A Advanced technique to improve the bonding arrangement on silicon surfaces to promote uniform nitridation 失效
标题翻译：先进的技术，以改善硅表面的结合布置，促进均匀的氮化
公开(公告)号：US5445999A
公开(公告)日：1995-08-29
申请号：US975767
申请日：1992-11-13
申请人： Randhir P. S. Thakur , Viju K. Mathews
发明人： Randhir P. S. Thakur , Viju K. Mathews
IPC分类号： H01L21/02 , H01L21/28 , H01L21/318 , H01L21/321 , H01L29/51 , H01L21/465
CPC分类号： H01L21/28202 , H01L21/3185 , H01L21/3211 , H01L29/518 , H01L28/40 , Y10S148/017
摘要： The present invention teaches a method for fabricating an ultrathin uniform dielectric layer over a silicon or polysilicon semiconductor substrate. The method entails first providing a substrate having a conductive area into a chamber. Subsequently, the first conductive material is destabilized by introducing it to reactive gas and radiant energy in situ. The reactive gas can be Ar-H.sub.2, H.sub.2, GeH.sub.4 or NF.sub.3 gas. The radiant energy source can be ultraviolet ("UV") or Tungsten Halogen lamps preferably having an approximate range of 0.2 to 1.6 .mu.m to provide heat of approximately 850.degree. to 1150.degree. C. for approximately 10 to 60 seconds at a vacuum pressure range of 10.sup.-10 Torr to atmospheric pressure. This process removes the native oxide and breaks the molecular clusters present on the silicon or polysilicon surface. Thereafter, a first dielectric layer having a substantially uniform thickness forms directly above the substrate by the in situ introduction of NH.sub.3 with the radiant energy generating heat of approximately 850.degree. to 1150.degree. C. for approximately 10 to 60 seconds at a vacuum pressure range of 10.sup.-10 Torr to atmospheric pressure. Finally, a second silicon nitride layer is deposited by low pressure chemical vapor deposition or plasma nitridation to create a combined thickness of both dielectric layers of 40 to 100 .ANG..
摘要翻译：本发明教导了一种在硅或多晶硅半导体衬底上制造超薄均匀介电层的方法。该方法需要首先将具有导电区域的基板提供到室中。随后，第一导电材料通过将其引入反应气体和原位辐射能而不稳定。反应气体可以是Ar-H2，H2，GeH4或NF3气体。辐射能源可以是紫外线（“UV”）或钨卤素灯，优选具有0.2至1.6μm的近似范围，以在真空压力范围内提供约850至1150℃的热量约10至60秒 10-10乇至大气压。该方法除去天然氧化物并破坏存在于硅或多晶硅表面上的分子簇。此后，具有基本上均匀厚度的第一电介质层通过在真空压力范围内原位引入NH 3，辐射能产生的热量约为850〜1150℃直接形成在基板的上方大约10至60秒 10-10乇至大气压。最后，通过低压化学气相沉积或等离子体氮化沉积第二氮化硅层，以产生40至100安培层的两个电介质层的组合厚度。

5. 发明授权

US07253052B2 Method for forming a storage cell capacitor compatible with high dielectric constant materials 有权
公开(公告)号：US07253052B2
公开(公告)日：2007-08-07
申请号：US10896442
申请日：2004-07-22
申请人： Pierre C. Fazan , Viju K. Mathews
发明人： Pierre C. Fazan , Viju K. Mathews
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L27/11502 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L27/11507 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , H01L28/91 , Y10T29/435 , Y10T29/49165
摘要： Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the first portion, the insulative layer encompassing a sidewall of the second portion. The method may further include forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein the first portion and the second portion are different materials. In an embodiment, the second portion is a diffusion barrier layer and the third portion is an oxidation resistant layer. In an embodiment, the method includes encompassing a lower sidewall of the third portion with the insulative layer.

6. 发明授权

US06791131B1 Method for forming a storage cell capacitor compatible with high dielectric constant materials 有权
标题翻译：用于形成与高介电常数材料兼容的存储单元电容器的方法
公开(公告)号：US06791131B1
公开(公告)日：2004-09-14
申请号：US09489954
申请日：2000-01-24
申请人： Pierre C. Fazan , Viju K. Mathews
发明人： Pierre C. Fazan , Viju K. Mathews
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L21/7687 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L27/11507 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/75 , H01L28/91 , Y10T29/435 , Y10T29/49165
摘要： The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewall of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is formed in the recess and the top surface of the barrier layer is recessed below the top surface of the oxide or oxide/nitride layer. The process continued with a formation of an oxidation resistant conductive layer and the deposition of a further oxide layer to fill remaining portions of the recess. The oxidation resistant conductive layer is planarized to expose the oxide or oxide/nitride layer and the oxide layers are then etched to expose the top surface and vertical portions of the oxidation resistant conductive layer. Next a dielectric layer having a high dielectric constant is formed to overlie the storage node electrode and a cell plate electrode is fabricated to overlie the dielectric layer.
摘要翻译：本发明是具有存储节点电极的存储单元电容器，该存储节点电极包括介于导电插塞和抗氧化层之间的阻挡层。在具有高介电常数的介电层的沉积和退火期间，厚的绝缘层保护阻挡层的侧壁。该方法包括在诸如氧化物或氧化物/氮化物的绝缘材料的厚层中形成导电插塞。导电插塞从厚绝缘层的平坦化顶表面凹陷。阻挡层形成在凹部中，并且阻挡层的顶表面凹陷在氧化物或氧化物/氮化物层的顶表面下方。该过程继续形成抗氧化导电层和沉积另外的氧化物层以填充凹部的剩余部分。将抗氧化导电层平坦化以暴露氧化物或氧化物/氮化物层，然后蚀刻氧化物层以暴露抗氧化导电层的顶表面和垂直部分。接下来，形成具有高介电常数的介电层，覆盖存储节点电极，并且制造单元板电极以覆盖介电层。

7. 发明授权

US6156612A Methods of forming field oxide and active area regions on a semiconductive substrate 失效
标题翻译：在半导体衬底上形成场氧化物和有源区域的方法
公开(公告)号：US6156612A
公开(公告)日：2000-12-05
申请号：US432431
申请日：1999-11-02
申请人： Viju K. Mathews
发明人： Viju K. Mathews
IPC分类号： H01L21/762 , H01L21/76 , H01L21/265
CPC分类号： H01L21/76202
摘要： Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked by the oxidation mask. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. In accordance with a first implementation, a portion of the semiconductive substrate is removed after removal of the oxidation mask but before the formation and removal of a sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird's beak region which is subsequently filled in with material when the sacrificial oxide layer is formed. In accordance with a second implementation, a portion of the semiconductive substrate is removed after formation and removal of the sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird's beak region which is subsequently filled in with material when the gate dielectric layer is formed.
摘要翻译：描述形成场氧化物区域和相邻有源区域区域的方法。半导体衬底用氧化掩模掩蔽，而衬底的相邻区域保持未被氧化掩模掩蔽。将衬底暴露于有效地在相邻区域中形成场氧化物区域的条件。场氧化物区域具有朝向有源区域延伸的鸟嘴区域。根据第一实施方案，在去除氧化掩模之后但在形成和去除牺牲氧化物层之前去除半导体衬底的一部分。根据该实施方案，半导体衬底材料的去除在鸟喙区域下形成底切区域，随后在形成牺牲氧化物层时填充材料。根据第二实施例，在形成和去除牺牲氧化物层之后，去除半导体衬底的一部分。根据该实施方式，半导体基板材料的去除在鸟的喙部区域形成底切区域，随后在形成栅极电介质层时填充材料。

8. 发明授权

US5994203A Process for stress reduction in silicon during field isolation 失效
标题翻译：在场隔离期间硅中应力降低的过程
公开(公告)号：US5994203A
公开(公告)日：1999-11-30
申请号：US607946
申请日：1996-02-28
申请人： Viju K. Mathews
发明人： Viju K. Mathews
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： A new polysilicon-buffered field isolation process provides reduced stress during field oxidation and reduced bird's beak. Prior to forming the LOCOS masking stack conventionally used for field isolation, a polysilicon buffer layer is first formed on the semiconductor wafer. The polysilicon buffer layer relieves stress between the masking stack and semiconductor wafer similar to conventional Poly-buffered LOCOS processes, but additionally provides sacrificial silicon into which the bird's beak region extends. Subsequent deprocessing of mask and buffer layers removes a significant portion of the bird's beak region, thereby providing active areas having improved physical and electrical characteristics.
摘要翻译：新的多晶硅缓冲场隔离工艺在场氧化和减少鸟的喙中减少了应力。在形成常规用于场隔离的LOCOS掩模堆叠之前，首先在半导体晶片上形成多晶硅缓冲层。多晶硅缓冲层减轻了掩蔽叠层和半导体晶片之间的压力，类似于传统的多缓冲LOCOS工艺，但另外还提供了鸟嘴区延伸的牺牲硅。掩模和缓冲层的后续去处理除去鸟的喙区域的相当大部分，从而提供具有改善的物理和电特性的有源区域。

9. 发明授权

US5933754A Semiconductor processing method of forming an electrically conductive contact plug 失效
标题翻译：形成导电接触插头的半导体加工方法
公开(公告)号：US5933754A
公开(公告)日：1999-08-03
申请号：US874642
申请日：1997-06-13
申请人： Viju K. Mathews , Nanseng Jeng , Pierre C. Fazan
发明人： Viju K. Mathews , Nanseng Jeng , Pierre C. Fazan
IPC分类号： H01L21/28 , H01L21/768 , H01L23/14 , H01L23/522 , H01L21/308
CPC分类号： H01L21/76843 , H01L21/76804 , H01L23/5226 , H01L2924/0002
摘要： A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer of conductive material atop the wafer and to within the facet etched contact opening to fill the contact opening; and h) etching the conductive material and first material layer inwardly to at least the angled sidewalls' inner base to define an electrically conductive contact plug which electrically connects with the substrate.
摘要翻译：相对于晶片形成导电接触插塞的半导体处理方法包括：a）提供要进行电连接的基板; b）在基板顶部沉积一层第一材料至所选择的厚度; c）图案掩蔽第一材料层以形成所需的接触开口; d）蚀刻通过第一材料层以形成通过其与基板电连接的接触开口，接触开口具有最外区域; e）在蚀刻之后形成接触开口，从第一材料层去除掩模; f）在从第一材料层去除掩模之后，相对于接触开口小面溅射蚀刻到第一材料层中以提供向外成角度的侧壁，这有效地加宽了接触开口最外区域，向外成角度的侧壁具有内部基部，与原来的接触开口; g）在晶片顶部和面蚀刻的接触开口内沉积导电材料层以填充接触开口; 以及h）将所述导电材料和所述第一材料层向内蚀刻到至少所述成角度的侧壁的内部基底，以限定与所述基底电连接的导电接触插塞。

10. 发明授权

US5895268A High pressure nitridation of tungsten 失效
标题翻译：钨的高压氮化
公开(公告)号：US5895268A
公开(公告)日：1999-04-20
申请号：US617208
申请日：1996-03-18
申请人： Viju K. Mathews
发明人： Viju K. Mathews
IPC分类号： H01L21/285 , H01L21/321 , H01L21/44
CPC分类号： H01L21/321 , H01L21/28568
摘要： Disclosed is a method for forming a refractory metal nitride layer which is highly suitable for diffusion barrier formation in CMOS structures. The process comprises first, forming a refractory metal layer and patterning therefrom a tungsten plug. The tungsten plug is then placed in a furnace where it is heated in an environment containing nitrogen at a high pressure. The high pressure allows efficient tungsten nitride formation at a low temperature so as to form tungsten nitride. In one embodiment, the furnace environment comprises ammonia, the pressure is about 25 atmospheres, and the temperature is about 500.degree. C. The tungsten nitride is a diffusion barrier that is formed between a tungsten plug and a superadjacent aluminum interconnect line that is deposited thereover in a CMOS memory structure.
摘要翻译：公开了一种形成耐高温金属氮化物层的方法，该方法非常适用于CMOS结构中的扩散阻挡层形成。该方法包括首先形成难熔金属层，并由此形成钨塞。然后将钨塞放置在炉中，在炉中在高压环境中加氮。高压允许在低温下形成有效的氮化钨以形成氮化钨。在一个实施方案中，炉环境包括氨，压力为约25大气压，温度为约500℃。氮化钨是形成在钨插塞和沉积在其上的超级相邻铝互连线之间的扩散阻挡层在CMOS存储器结构中。

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