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    • 3. 发明授权
    • Power conservation with a synchronous master-slave serial data bus
    • 使用同步主从串行数据总线进行省电
    • US06557063B1
    • 2003-04-29
    • US09868294
    • 2002-06-04
    • Wei WangVictor MartenIoannis Milios
    • Wei WangVictor MartenIoannis Milios
    • G06F1300
    • H04L7/0008H04L1/1803
    • A system is described in which the Master can stop its clock and go into a low-power state (for power conservation reasons) at arbitrary times. Before going into the stopped-clock or low-power mode, the Master checks that the serial bus is idle (defined as both Clock and Data lines being “High”). A latch circuit is provided which is active when them aster is in low-power mode. The latch circuit watches for the very first negative-going clock pulse (from the slave), and its configuration is such that when latched, it holds the clock line low. Holding the clock line low prompts the slave to discontinue efforts to send the data. Stated differently, the slave will not conclude that it had successfully sent its data, and this prompts the slave to retain a copy of its data for later resending.
    • 描述了一种系统,其中主机可以在任意时间停止其时钟并进入低功率状态(为了省电原因)。 在进入停止时钟或低功耗模式之前,主器件检查串行总线是否空闲(定义为时钟和数据线均为“高”)。 提供一个锁存电路,当它们处于低功率模式时,该电路是有效的。 锁存电路监视第一个负向时钟脉冲(从从器件),其配置使得当锁存时,它将时钟线保持为低电平。 保持时钟线为低提示从机停止发送数据的努力。 换句话说,奴隶不会断定它已成功发送其数据,并且这提示从属方保留其数据的副本以供稍后重新发送。
    • 4. 发明授权
    • Clock stretcher and level shifter with small component count and low power consumption
    • 时钟延长器和电平移位器,具有小的元件数量和低功耗
    • US06239644B1
    • 2001-05-29
    • US09445191
    • 2000-03-15
    • Victor MartenIoannis MiliosWei Wang
    • Victor MartenIoannis MiliosWei Wang
    • H03L500
    • H03K19/018507G06F1/08G06F13/4217Y02D10/14Y02D10/151
    • A clock stretching circuit (110) mites between a synchronous bus (112) and a microcontroller (124) which is asleep most of the time to save electrical power. The bus is of a type in which a slow bus device can cause the sender of data to “hold” the data until the slow device is up to speed. The stretching circuit (110) is of small component count and low power consumption, and there is no requirement for a continuous clock. In one embodiment is comprised of a triple analog switch (120, 121, 122) and a very small number of additional components. In another embodiment a dual four-position multiplexer (162, 163) is employed. In still another embodiment, four transistors (210, 212, 213, 215) are used with handful of additional components. A level shifter (220, 221, 222, 223) including an MOSFET and a large-value resistor help to minimize power drain within the bus device. The components can be external to an off-the-shelf microcontroller or can be included in an IC that also contains an embedded microcontroller.
    • 时钟延长电路(110)在同步总线(112)和微处理器(124)之间ites),大部分时间都在睡眠以节省电力。 总线是一种类型,其中慢速总线设备可以使数据的发送者“保持”数据,直到慢速设备达到速度。 拉伸电路(110)的元件数量小,功耗低,不需要连续时钟。 在一个实施例中,包括三重模拟开关(120,121,122)和非常少量的附加组件。 在另一个实施例中,采用双重四位多路复用器(162,163)。 在另一个实施例中,四个晶体管(210,212,213,215)与少数附加组件一起使用。 包括MOSFET和大值电阻的电平移位器(220,221,222,223)有助于最小化总线装置内的功率消耗。 这些组件可以在现成的微控制器外部,也可以包含在还包含嵌入式微控制器的IC中。
    • 9. 发明授权
    • Termination apparatus and method for planar components on printed circuit boards
    • 印刷电路板上平面部件的端接装置和方法
    • US07944710B2
    • 2011-05-17
    • US12528443
    • 2008-10-06
    • Victor MartenAakar PatelMark Vanstone
    • Victor MartenAakar PatelMark Vanstone
    • H05K1/11
    • H05K3/363H05K1/165H05K3/3447H05K3/368H05K2201/096H05K2201/10303H05K2201/10666H05K2201/10871Y10T29/49126Y10T29/49153Y10T29/49165
    • The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.
    • 本公开涉及使用相对较小的空间并提供低电阻连接将平面感应元件的绕组PCB有效地端接到主PCB。 所公开的方法特别适用于其中几个绕组PCB,和/或绕组PCB和主PCB都由磁路部件封闭的平面结构。 这些方法允许绕组PCB简单地搁置在主PCB或其他绕组PCB上,没有任何间隙。 本公开采用配套的导电环形环,其具有可选的互锁端子销,其允许两个PCB固定地耦合在一起,同时保持两个PCB的焊接掩模层之间的最小距离,以防止形成不需要的电连接 在两个PCB之间。 焊接用于确保配合环形圈和可选端子销的每个组件中的有效耦合。