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    • 1. 发明申请
    • Area efficient arrangement of interface devices within an integrated circuit
    • 集成电路内接口设备的区域高效布置
    • US20120179893A1
    • 2012-07-12
    • US12929236
    • 2011-01-10
    • Vikas MishraBingda Brandon Wang
    • Vikas MishraBingda Brandon Wang
    • G06F15/80G06F9/06
    • H01L23/5286H01L27/0207H01L2924/0002H01L2924/00
    • An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.
    • 公开了一种集成电路,其包括:包括逻辑电路的核心:用于向处理核心和从处理核心传送信号的多个接口装置,所述多个接口装置包括两种类型的接口装置:一种类型是用于传送的电力接口装置 权力到核心; 并且第二类型是用于在所述集成电路外部的所述核心和装置之间传输数据信号的信号接口装置; 其中所述多个接口装置布置成两排,朝向所述芯的外边缘的外排和所述外排内的更靠近所述芯的中心的内排,所述内排包括所述两种类型的接口装置中的一种, 外部行包括两种类型的接口设备中的另一种。
    • 3. 发明授权
    • Area efficient arrangement of interface devices within an integrated circuit
    • 集成电路内接口设备的区域高效布置
    • US08549257B2
    • 2013-10-01
    • US12929236
    • 2011-01-10
    • Vikas MishraBingda Brandon Wang
    • Vikas MishraBingda Brandon Wang
    • G06F15/00G06F9/06
    • H01L23/5286H01L27/0207H01L2924/0002H01L2924/00
    • An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.
    • 公开了一种集成电路,其包括:包括逻辑电路的核心:用于向处理核心和从处理核心传送信号的多个接口装置,所述多个接口装置包括两种类型的接口装置:一种类型是用于传送的电力接口装置 权力到核心; 并且第二类型是用于在所述集成电路外部的所述核心和装置之间传输数据信号的信号接口装置; 其中所述多个接口装置布置成两排,朝向所述芯的外边缘的外排和所述外排内的更靠近所述芯的中心的内排,所述内排包括所述两种类型的接口装置中的一种, 外部行包括两种类型的接口设备中的另一种。