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1. 发明授权

US08549257B2 Area efficient arrangement of interface devices within an integrated circuit 失效
标题翻译：集成电路内接口设备的区域高效布置
公开(公告)号：US08549257B2
公开(公告)日：2013-10-01
申请号：US12929236
申请日：2011-01-10
申请人： Vikas Mishra , Bingda Brandon Wang
发明人： Vikas Mishra , Bingda Brandon Wang
IPC分类号： G06F15/00 , G06F9/06
CPC分类号： H01L23/5286 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.
摘要翻译：公开了一种集成电路，其包括：包括逻辑电路的核心：用于向处理核心和从处理核心传送信号的多个接口装置，所述多个接口装置包括两种类型的接口装置：一种类型是用于传送的电力接口装置权力到核心; 并且第二类型是用于在所述集成电路外部的所述核心和装置之间传输数据信号的信号接口装置; 其中所述多个接口装置布置成两排，朝向所述芯的外边缘的外排和所述外排内的更靠近所述芯的中心的内排，所述内排包括所述两种类型的接口装置中的一种，外部行包括两种类型的接口设备中的另一种。

2. 发明申请

US20120179893A1 Area efficient arrangement of interface devices within an integrated circuit 失效
标题翻译：集成电路内接口设备的区域高效布置
公开(公告)号：US20120179893A1
公开(公告)日：2012-07-12
申请号：US12929236
申请日：2011-01-10
申请人： Vikas Mishra , Bingda Brandon Wang
发明人： Vikas Mishra , Bingda Brandon Wang
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： H01L23/5286 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.
摘要翻译：公开了一种集成电路，其包括：包括逻辑电路的核心：用于向处理核心和从处理核心传送信号的多个接口装置，所述多个接口装置包括两种类型的接口装置：一种类型是用于传送的电力接口装置权力到核心; 并且第二类型是用于在所述集成电路外部的所述核心和装置之间传输数据信号的信号接口装置; 其中所述多个接口装置布置成两排，朝向所述芯的外边缘的外排和所述外排内的更靠近所述芯的中心的内排，所述内排包括所述两种类型的接口装置中的一种，外部行包括两种类型的接口设备中的另一种。

3. 发明申请

US20090153210A1 Maintaining output I/O signals within an integrated circuit with multiple power domains 有权
标题翻译：在具有多个电源域的集成电路中维护输出I / O信号
公开(公告)号：US20090153210A1
公开(公告)日：2009-06-18
申请号：US12000573
申请日：2007-12-13
申请人： Bingda Brandon Wang , George Shing , Puneet Sawhney
发明人： Bingda Brandon Wang , George Shing , Puneet Sawhney
IPC分类号： H03K3/02
CPC分类号： G06F1/32 , Y10T307/406
摘要： An integrated circuit is provided with a power domain PD0, PD1, PD2, PD3 which can be selectively powered-up or powered-down. An output circuitry 8 serving to buffer a signal 12 generated by the core circuitry 10 within such a power domain has its own output power supply voltage IOVdd. An adaptive voltage sensing circuit 24 senses when the core power supply voltage to the core circuitry 10 falls below a threshold level and generates a voltage-low signal. If output signal retention has been preselected to be active for the output signal concerned, then the output circuitry 8 responds to the voltage-low signal by maintaining the output signal state (output signal driven low, output signal driven high or output signal in a high impedance drive state). The retention mode is preselected by a on-shot pulse with its value stored within a mode latch 24 indicating whether or not retention is required. Thus, when the adapted voltage sensing circuitry 24 itself senses the voltage level for the core circuitry 10 falling below the threshold, it activates the retention operation.
摘要翻译：集成电路具有电源域PD0，PD1，PD2，PD3，可以选择上电或掉电。用于缓冲由核心电路10在这样的电源域内产生的信号12的输出电路8具有其自己的输出电源电压IOVdd。自适应电压感测电路24检测到核心电路10的核心电源电压何时下降到阈值以下并产生低电压信号。如果输出信号保持被预选为有效的输出信号，则输出电路8通过维持输出信号状态（输出信号驱动为低电平，输出信号驱动为高电平或输出信号为高电平）来响应电压 - 低电平信号阻抗驱动状态）。保留模式由一个触发脉冲预先选择，其值存储在模式锁存器24中，指示是否需要保留。因此，当适应的电压感测电路24本身感测到核心电路10的阈值以下的电压电平时，它启动保持操作。

4. 发明授权

US08024690B2 Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices 有权
标题翻译：用于确定互连电路中数据路径的路由的方法，系统和计算机程序产品，其提供用于连接到第一设备的窄接口和用于连接到分布式多个另外的设备的宽接口
公开(公告)号：US08024690B2
公开(公告)日：2011-09-20
申请号：US12153448
申请日：2008-05-19
申请人： Kostadin Gitchev , Bingda Brandon Wang
发明人： Kostadin Gitchev , Bingda Brandon Wang
IPC分类号： G06F17/50 , G06F9/455 , H01L25/00
CPC分类号： G06F17/5077
摘要： A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The method includes the steps of defining a plurality of cells to be provided along the wide interface of the circuitry, further devices being associated with at least one of the cells, and defining the circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns. The method includes the steps of: providing a predetermined set of tiles, each tile providing a predetermined wiring layout, and for each block, applying predetermined rules to determine one of the tiles to be used to implement that block, where the rules take into account the location of the block in the array and any association between the further devices and the cells.
摘要翻译：提供了一种用于确定用于集成电路的互连电路中的数据路径的路由的系统，方法和计算机程序产品。该方法包括以下步骤：定义要沿着电路的宽接口提供的多个单元，其它设备与至少一个单元相关联，并且将电路定义为以行和列形成的块阵列，其中，每个单元格邻接其中一列。该方法包括以下步骤：提供预定的瓦片集合，每个瓦片提供预定布线布局，并且对于每个块，应用预定规则来确定要用于实施该块的瓦片之一，其中规则考虑阵列中的块的位置以及其他设备和单元之间的任何关联。

5. 发明授权

US07839016B2 Maintaining output I/O signals within an integrated circuit with multiple power domains 有权
标题翻译：在具有多个电源域的集成电路中维护输出I / O信号
公开(公告)号：US07839016B2
公开(公告)日：2010-11-23
申请号：US12000573
申请日：2007-12-13
申请人： Bingda Brandon Wang , George Shing , Puneet Sawhney
发明人： Bingda Brandon Wang , George Shing , Puneet Sawhney
IPC分类号： H02J3/12
CPC分类号： G06F1/32 , Y10T307/406
摘要： An integrated circuit is provided with a power domain which can be selectively powered-up or powered-down. An output circuitry serving to buffer a signal generated by the core circuitry within such a power domain has its own output power supply voltage. An adaptive voltage sensing circuit senses when the core power supply voltage to the core circuitry falls below a threshold level and generates a voltage-low signal. If output signal retention has been preselected to be active for the output signal concerned, then the output circuitry responds to the voltage-low signal by maintaining the output signal state (output signal driven low, output signal driven high or output signal in a high impedance drive state). The retention mode is preselected by a pulse with its value stored within a mode latch indicating whether or not retention is required. Thus, when the adapted voltage sensing circuitry itself senses the voltage level for the core circuitry falling below the threshold, it activates the retention operation.
摘要翻译：集成电路具有能够选择上电或掉电的电源域。用于缓冲由这样的功率域内的核心电路产生的信号的输出电路具有其自己的输出电源电压。自适应电压感测电路感测到核心电路的核心电源电压何时下降到阈值以下并产生低电压信号。如果输出信号保持被预选为有效的输出信号，则输出电路通过保持输出信号状态（输出信号驱动为低电平，输出信号驱动为高电平或高阻抗输出信号）来响应电压 - 低电平信号驱动状态）。保持模式由脉冲预先选择，其值存储在模式锁存器中，指示是否需要保留。因此，当适应的电压感测电路本身感测到核心电路的电压电平低于阈值时，它激活保持操作。

6. 发明授权

US08680900B2 Self-initializing on-chip data processing apparatus and method of self-initializing an on-chip data processing apparatus 有权
标题翻译：自初始化片上数据处理装置以及对片上数据处理装置进行自初始化的方法
公开(公告)号：US08680900B2
公开(公告)日：2014-03-25
申请号：US13571753
申请日：2012-08-10
申请人： Bingda Brandon Wang , Kostadin Gitchev
发明人： Bingda Brandon Wang , Kostadin Gitchev
IPC分类号： H03L7/00
CPC分类号： G06F1/30 , G06F1/08
摘要： An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency.
摘要翻译：片上数据处理装置具有从供电电压的范围中选择的工作电源电压，并且具有电压电平检测电路，配置成确定工作电源电压的电平。电压电平检测电路包括响应于参考电压变化的自适应电路。锁相环电路被配置为从工作电源电压产生源时钟信号，以接收电压电平选择信号，以根据电压电平选择信号选择源时钟信号的目标频率，并且相位锁定源时钟信号在目标频率上。初始化电路被配置为在锁相环电路已经将目标频率上的源时钟信号锁相之后，根据所述工作电源电压的电平来初始化用于数据处理的片上数据处理装置。

7. 发明申请

US20090288056A1 Method, system and computer program product for determining routing of data paths in interconnect circuitry 有权
标题翻译：用于确定互连电路中数据路径路由的方法，系统和计算机程序产品
公开(公告)号：US20090288056A1
公开(公告)日：2009-11-19
申请号：US12153448
申请日：2008-05-19
申请人： Kostadin Gitchev , Bingda Brandon Wang
发明人： Kostadin Gitchev , Bingda Brandon Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The interconnect circuitry on a first side provides a narrow interface for connection to a first device, and on a second side provides a wide interface for connection to a distributed plurality of further devices. Each data path is associated with one of the further devices and provides a connection through the interconnect circuitry between that associated further device and the first device. The method comprises the steps of defining a plurality of cells to be provided along the wide interface, each of the further devices being associated with at least one of the cells, and defining the interconnect circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns. Further, the method includes the steps of providing a predetermined set of tiles, each tile providing a predetermined wiring layout, and for each block, applying predetermined rules to determine one of the tiles to be used to implement that block. The predetermined rules take into account the location of the block in the array and the association between the plurality of further devices and the plurality of cells, ensuring that each data path provided by the interconnect circuitry has the same propagation delay. By such an approach, a structured routing method is provided that uses predetermined tiles enabling a layout design for the interconnect circuitry to be readily produced whilst ensuring that the propagation delays are matched for each of the data paths within the interconnect circuitry.
摘要翻译：提供了一种用于确定用于集成电路的互连电路中的数据路径的路由的系统，方法和计算机程序产品。第一侧上的互连电路提供用于连接到第一设备的窄接口，并且在第二侧上提供用于连接到分布的多个另外的设备的宽接口。每个数据路径与其他设备中的一个相关联，并通过该相关联的另外的设备和第一设备之间的互连电路提供连接。该方法包括以下步骤：定义要沿宽接口提供的多个单元，每个其它设备与至少一个单元相关联，并将互连电路定义为以行和列形成的块阵列，每个单元格邻接其中一列。此外，该方法包括以下步骤：提供预定的瓦片集合，每个瓦片提供预定的布线布局，并且对于每个块，应用预定的规则来确定要用于实现该块的瓦片之一。预定规则考虑到阵列中的块的位置以及多个另外的设备和多个小区之间的关联，确保由互连电路提供的每个数据路径具有相同的传播延迟。通过这种方法，提供了使用预定瓦片的结构化路由方法，其使得能够容易地产生用于互连电路的布局设计，同时确保对互连电路内的每个数据路径的传播延迟进行匹配。

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