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1. 发明授权

US09324634B2 Semiconductor interconnect structure having a graphene-based barrier metal layer 有权
标题翻译：具有石墨烯阻挡金属层的半导体互连结构
公开(公告)号：US09324634B2
公开(公告)日：2016-04-26
申请号：US13291470
申请日：2011-11-08
申请人： Junjing Bao , Shaoning Yao , Xuesong Li , Samuel S. S. Choi
发明人： Junjing Bao , Shaoning Yao , Xuesong Li , Samuel S. S. Choi
IPC分类号： H01L23/482 , H01L23/532 , H01L21/768 , H01L23/48 , B82Y40/00
CPC分类号： H01L23/4827 , B82Y40/00 , H01L21/76834 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L23/481 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.
摘要翻译：一种用于制造具有增强的性能和可靠性的互连结构的互连结构和方法，所述互连结构和方法通过利用基于石墨烯的阻挡金属层来阻挡从电介质层渗入互连结构中的氧，并阻止从互连结构到电介质层的铜扩散，被披露。在电介质层中形成至少一个开口。形成设置在电介质层上的基于石墨烯的阻挡金属层。形成设置在石墨烯阻挡金属层上的种子层。形成设置在种子层上的电镀铜层。形成平坦化表面，其中除去石墨烯基阻挡金属层，籽晶层和电镀铜层的一部分。此外，形成设置在平坦化表面上的覆盖层。

2. 发明授权

US08237246B2 Deep trench crackstops under contacts 失效
标题翻译：深沟槽裂缝下的接触
公开(公告)号：US08237246B2
公开(公告)日：2012-08-07
申请号：US12689479
申请日：2010-01-19
申请人： Matthew S. Angyal , Lawrence A. Clevenger , Vincent J. McGahay , Satyanarayana V. Nitta , Shaoning Yao
发明人： Matthew S. Angyal , Lawrence A. Clevenger , Vincent J. McGahay , Satyanarayana V. Nitta , Shaoning Yao
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L29/0657 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.
摘要翻译：形成在半导体衬底的接触电平下方的深沟槽作为裂纹，在晶片的管芯区域或划线区域中起作用，并且可以设置成距它们旨在保护的器件的距离增加的行，并且可以位于在互连堆叠层中的格子工作裂纹结构下。深沟槽可以保持未填充，或者可以用介电材料或导体填充。深沟槽可以具有大约1微米至100微米的衬底的深度和约10nm至10微米的宽度。

3. 发明授权

US08623673B1 Structure and method for detecting defects in BEOL processing 失效
标题翻译：用于检测BEOL处理缺陷的结构和方法
公开(公告)号：US08623673B1
公开(公告)日：2014-01-07
申请号：US13572720
申请日：2012-08-13
申请人： Thomas W. Dyer , Tze-Man Ko , Yiheng Xu , Shaoning Yao
发明人： Thomas W. Dyer , Tze-Man Ko , Yiheng Xu , Shaoning Yao
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： H01L22/34 , H01L22/30
摘要： A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region. Embodiments may further include methods of manufacturing said test structures and methods of utilizing said test structures to monitor back end processes and determine if such processes are within specification limits.
摘要翻译：一种用于监测过程均匀性的测试结构和方法。本发明的实施例包括具有第一金属化层的第一金属化层，在第一金属化层上形成的第二金属化层，第一金属化层中的缺陷产生区，在产生缺陷的第二金属化层中的缺陷分散区的测试结构地区; 以及与所述缺陷分散区域相邻的所述第二金属化层中的缺陷检测区域。示例性实施例的缺陷产生区域可以具有零图案密度，均匀的非零图案密度或非均匀非零图案密度。缺陷检测区域可以包括诸如梳状蛇形结构的测试图案。实施例可以包括多于一个缺陷产生区域，多于一个缺陷分散区域或多于一个缺陷检测区域。实施例还可以包括制造所述测试结构的方法以及利用所述测试结构来监测后端处理并确定这些过程是否在规定范围内的方法。

4. 发明申请

US20130113102A1 SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE-BASED BARRIER METAL LAYER 有权
公开(公告)号：US20130113102A1
公开(公告)日：2013-05-09
申请号：US13291470
申请日：2011-11-08
申请人： Junjing Bao , Shaoning Yao , Xuesong Li , Samuel S. S. Choi
发明人： Junjing Bao , Shaoning Yao , Xuesong Li , Samuel S. S. Choi
IPC分类号： H01L23/538 , H01L21/768 , B82Y30/00 , B82Y40/00
CPC分类号： H01L23/4827 , B82Y40/00 , H01L21/76834 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L23/481 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

5. 发明申请

US20100200960A1 DEEP TRENCH CRACKSTOPS UNDER CONTACTS 失效
标题翻译： DEEP TRENCH CRACKSTOPS UNDER联系人
公开(公告)号：US20100200960A1
公开(公告)日：2010-08-12
申请号：US12689479
申请日：2010-01-19
申请人： Matthew S. Angyal , Lawrence A. Clevenger , Vincent J. McGahay , Satyanarayana V. Nitta , Shaoning Yao
发明人： Matthew S. Angyal , Lawrence A. Clevenger , Vincent J. McGahay , Satyanarayana V. Nitta , Shaoning Yao
IPC分类号： H01L23/544 , H01L21/302
CPC分类号： H01L23/585 , H01L29/0657 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.
摘要翻译：形成在半导体衬底的接触电平下方的深沟槽作为裂纹，在晶片的管芯区域或划线区域中起作用，并且可以设置成距它们旨在保护的器件的距离增加的行，并且可以位于在互连堆叠层中的格子工作裂纹结构下。深沟槽可以保持未填充，或者可以用介电材料或导体填充。深沟槽可以具有大约1微米至100微米的衬底的深度和约10nm至10微米的宽度。

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