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1. 发明申请

US20070241456A1 Conductive structure for electronic device 审中-公开
标题翻译：电子设备导电结构
公开(公告)号：US20070241456A1
公开(公告)日：2007-10-18
申请号：US11498146
申请日：2006-08-03
申请人： Tze-Hsiang Chao , Chung Ju Wu
发明人： Tze-Hsiang Chao , Chung Ju Wu
IPC分类号： H01L23/48
CPC分类号： H01L23/5225 , H01L23/5223 , H01L24/06 , H01L2224/05093 , H01L2224/05553 , H01L2224/48091 , H01L2224/4813 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A conductive structure for electronic device includes at least a first conductor, at least a second conductor and a conductive material for connecting the first conductor and the second conductor.
摘要翻译：用于电子器件的导电结构包括至少第一导体，至少第二导体和用于连接第一导体和第二导体的导电材料。

2. 发明申请

US20070096774A1 System and method for clock switching 有权
标题翻译：时钟切换的系统和方法
公开(公告)号：US20070096774A1
公开(公告)日：2007-05-03
申请号：US11261880
申请日：2005-10-28
申请人： Chia-hao Yang , Tze-hsiang Chao
发明人： Chia-hao Yang , Tze-hsiang Chao
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.
摘要翻译：描述了在集成电路领域中应用的时钟切换系统。相位插值器将输入时钟信号转换成时钟A和时钟B，其间具有相位差，并发送时钟A和时钟B。连接到相位插值器的开关指令单元接收作为触发信号的时钟A或时钟B，用于触发开关指令单元，以在输出开关信号位于上升沿或下降沿时将输入切换信号变换为输出切换信号一个下降的边缘。连接到相位插值器和开关指令单元的选择装置根据来自开关指令单元的输出切换信号选择clock_A或clock_B，以输出由clock_A和clock_B组成的时钟切换信号。

3. 发明申请

US20070090862A1 APPARATUS AND METHOD OF CONTROLLING AND TUNING A FINE CALIBRATION FOR CLOCK SOURCE SYNCHRONIZATION IN DUAL LOOP OF HYBRID PHASE AND TIME DOMAIN 有权
标题翻译：控制和调谐混合相位和时域双环中时钟源同步的精细校准的装置和方法
公开(公告)号：US20070090862A1
公开(公告)日：2007-04-26
申请号：US11320254
申请日：2005-12-27
申请人： Tze-hsiang Chao , Chia-hao Yang , Chia-jung Liu
发明人： Tze-hsiang Chao , Chia-hao Yang , Chia-jung Liu
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812
摘要： An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signals and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signals. The controller controls the coarse calibration unit and the first fine calibration unit to align the feedback signal to the reference signal according to the indicating signal generated from the phase detector. The rotating detector rapidly tunes the phase difference between the feedback signal and the reference signal by adding a number of time delays to the feedback signal when the feedback signal and the reference signal are miss-aligned.
摘要翻译：描述了一种用于电子设备中的时钟源同步的混合相位和时域的双环控制和调谐时钟相位对准的装置和方法。粗略校准单元产生多个输出信号，输出信号之间具有多个固定相间隔。固定相位间隔中的至少一个等于完成360度，其除以输出信号的数量以覆盖完整360度的相位范围。连接到粗校准单元的第一精细校准单元通过耦合可编程延迟电路来延迟从粗校准单元生成的输出信号，以将反馈信号的相位调整到参考信号的相位。连接到第一精细校准单元的相位检测器用于检测参考和反馈信号之间的相位差，并输出与参考和反馈信号之间的相位差对应的指示信号。控制器控制粗略校准单元和第一精细校准单元，以根据从相位检测器产生的指示信号将反馈信号与参考信号对准。当反馈信号和参考信号错过对准时，旋转检测器通过向反馈信号添加多个时间延迟来快速调谐反馈信号和参考信号之间的相位差。

4. 发明授权

US07208403B2 Tile-based routing method of a multi-layer circuit board and related structure 有权
标题翻译：多层电路板的基于瓦片的布线方法及相关结构
公开(公告)号：US07208403B2
公开(公告)日：2007-04-24
申请号：US11277042
申请日：2006-03-21
申请人： Chung-Yi Fang , Tze-Hsiang Chao , Yi-Show Su
发明人： Chung-Yi Fang , Tze-Hsiang Chao , Yi-Show Su
IPC分类号： H01L21/44
CPC分类号： H05K1/112 , G06F17/5077 , H01L23/49822 , H01L23/49838 , H01L23/50 , H01L23/552 , H01L2924/0002 , H01L2924/15173 , H05K1/0219 , H05K2201/09227 , H05K2201/09236 , H05K2201/10674 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.
摘要翻译：一种用于从多个对应的缓冲垫中路由多个信号迹线的方法，用于在多层电路板上实现管芯包括利用位于管芯的周边区域中的多个保险杠垫; 利用位于模具的中心区域中的多个电源/接地保险杠垫; 在多层电路板的第一层中路由多个第一层迹线，分配对应于多个保险杠垫的多个信号迹线; 在多层电路板的第二层中路由多个第二层迹线，分配对应于多个保险杠焊盘的多个信号迹线; 将多个第一层迹线直接远离模具布置; 以及以不垂直于第一层迹线下方的转弯来路由多个第二层迹线。

5. 发明授权

US07043828B2 Tile-based routing method of a multi-layer circuit board 有权
标题翻译：多层电路板的基于瓦片的路由方法
公开(公告)号：US07043828B2
公开(公告)日：2006-05-16
申请号：US10604036
申请日：2003-06-23
申请人： Chung-Yi Fang , Tze-Hsiang Chao , Yi-Show Su
发明人： Chung-Yi Fang , Tze-Hsiang Chao , Yi-Show Su
IPC分类号： H05K3/36
CPC分类号： H05K1/112 , G06F17/5077 , H01L23/49822 , H01L23/49838 , H01L23/50 , H01L23/552 , H01L2924/0002 , H01L2924/15173 , H05K1/0219 , H05K2201/09227 , H05K2201/09236 , H05K2201/10674 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： A routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board. The multi-layer circuit board includes at least a first layer and a second layer. The method includes arranging the plurality of bumper pads based on a plurality of triangle units, routing a plurality of signal traces out of a plurality of corresponding bumper pads of in the first layer, routing a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer, and arranging a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.
摘要翻译：一种用于将多个信号迹线从多层电路板中的多个对应的保险杠垫中排列的布线方法。多层电路板至少包括第一层和第二层。该方法包括基于多个三角形单元布置多个保险杠垫，将多个信号迹线从第一层中的多个对应的缓冲垫中排出，将多个信号迹线从多个相应的保险杠第二层中的焊盘不与第一层中布线的多条信号迹线垂直平行，并且在第一层和第二层中的多条信号迹线之间布置多条屏蔽迹线。

6. 发明授权

US07411429B2 System and method for clock switching 有权
标题翻译：时钟切换的系统和方法
公开(公告)号：US07411429B2
公开(公告)日：2008-08-12
申请号：US11261880
申请日：2005-10-28
申请人： Chia-hao Yang , Tze-hsiang Chao
发明人： Chia-hao Yang , Tze-hsiang Chao
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.
摘要翻译：描述了在集成电路领域中应用的时钟切换系统。相位插值器将输入时钟信号转换成时钟A和时钟B，其间具有相位差，并发送时钟A和时钟B。连接到相位插值器的开关指令单元接收作为触发信号的时钟A或时钟B，用于触发开关指令单元，以在输出开关信号位于上升沿或下降沿时将输入切换信号变换为输出切换信号一个下降的边缘。连接到相位插值器和开关指令单元的选择装置根据来自开关指令单元的输出切换信号选择clock_A或clock_B，以输出由clock_A和clock_B组成的时钟切换信号。

7. 发明申请

US20060154402A1 TILE-BASED ROUTING METHOD OF A MULTI-LAYER CIRCUIT BOARD AND RELATED STRUCTURE 有权
标题翻译：多层电路板的基于路由的路由方法及相关结构
公开(公告)号：US20060154402A1
公开(公告)日：2006-07-13
申请号：US11277042
申请日：2006-03-21
申请人： Chung-Yi Fang , Tze-Hsiang Chao , Yi-Show Su
发明人： Chung-Yi Fang , Tze-Hsiang Chao , Yi-Show Su
IPC分类号： H01L21/50
CPC分类号： H05K1/112 , G06F17/5077 , H01L23/49822 , H01L23/49838 , H01L23/50 , H01L23/552 , H01L2924/0002 , H01L2924/15173 , H05K1/0219 , H05K2201/09227 , H05K2201/09236 , H05K2201/10674 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.
摘要翻译：一种用于从多个对应的缓冲垫中路由多个信号迹线的方法，用于在多层电路板上实现管芯包括利用位于管芯的周边区域中的多个保险杠垫; 利用位于模具的中心区域中的多个电源/接地保险杠垫; 在多层电路板的第一层中路由多个第一层迹线，分配对应于多个保险杠垫的多个信号迹线; 在多层电路板的第二层中路由多个第二层迹线，分配对应于多个保险杠焊盘的多个信号迹线; 将多个第一层迹线直接远离模具布置; 以及以不垂直于第一层迹线下方的转弯来路由多个第二层迹线。

8. 发明授权

US07183821B1 Apparatus and method of controlling clock phase alignment with dual loop of hybrid phase and time domain for clock source synchronization 有权
标题翻译：用于时钟源同步的混合相位和时域双环控制时钟相位对准的装置和方法
公开(公告)号：US07183821B1
公开(公告)日：2007-02-27
申请号：US11257258
申请日：2005-10-24
申请人： Tze-hsiang Chao , Chia-jung Liu
发明人： Tze-hsiang Chao , Chia-jung Liu
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812
摘要： An apparatus and a method of controlling clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of phase intervals therebetween. A predetermined phase angle is divided by the number of the output signals to generate one of the phase intervals. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signal and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signal. The controller controls the coarse calibration unit and the first fine calibration unit to align the feedback signal to the reference signal according to the indicating signal generated from the phase detector.
摘要翻译：描述了用于电子设备中的时钟源同步的混合相位和时域的双回路控制时钟相位对准的装置和方法。粗略校准单元产生多个输出信号，输出信号之间具有多个相位间隔。将预定的相位角除以输出信号的数量以产生相位间隔之一。连接到粗校准单元的第一精细校准单元通过耦合可编程延迟电路来延迟从粗校准单元生成的输出信号，以将反馈信号的相位调整到参考信号的相位。连接到第一精细校准单元的相位检测器用于检测参考和反馈信号之间的相位差，并输出与参考和反馈信号之间的相位差对应的指示信号。控制器控制粗略校准单元和第一精细校准单元，以根据从相位检测器产生的指示信号将反馈信号与参考信号对准。

9. 发明授权

US07034589B2 Multi-stage delay clock generator 失效
标题翻译：多级延迟时钟发生器
公开(公告)号：US07034589B2
公开(公告)日：2006-04-25
申请号：US10708373
申请日：2004-02-26
申请人： Tze-Hsiang Chao
发明人： Tze-Hsiang Chao
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/06 , G06F1/10 , H03L7/095
摘要： The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signal where a first delay cell among the plurality of delay cells receives an external clock signal, and each subsequent delay cell comprises a smaller delay step than the current delay cell; a phase detector, responsive to the external clock signal and a feedback clock signal, for generating a lock control signal; an integrator, responsive to the lock control signal, for generating the delay control signal; and a control unit for programming the delay cells.
摘要翻译：本发明提供一种多级延迟时钟发生器，包括：多个延迟单元，每个延迟单元响应于来自前一个延迟单元的延迟时钟信号和延迟控制信号而产生延迟信号给后续延迟单元，其中a 多个延迟单元中的第一延迟单元接收外部时钟信号，并且每个后续延迟单元包括比当前延迟单元更小的延迟步长; 响应于所述外部时钟信号和反馈时钟信号的相位检测器，用于产生锁定控制信号; 响应于所述锁定控制信号的积分器，用于产生所述延迟控制信号; 以及用于对延迟单元进行编程的控制单元。

10. 发明授权

US07202716B1 Apparatus and method of controlling and tuning a fine calibration for clock source synchronization in dual loop of hybrid phase and time domain 有权
标题翻译：在混合相位和时域的双回路中控制和调整精确校准用于时钟源同步的装置和方法
公开(公告)号：US07202716B1
公开(公告)日：2007-04-10
申请号：US11320254
申请日：2005-12-27
申请人： Tze-hsiang Chao , Chia-hao Yang , Chia-jung Liu
发明人： Tze-hsiang Chao , Chia-hao Yang , Chia-jung Liu
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812
摘要： An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signals and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signals. The controller controls the coarse calibration unit and the first fine calibration unit to align the feedback signal to the reference signal according to the indicating signal generated from the phase detector. The rotating detector rapidly tunes the phase difference between the feedback signal and the reference signal by adding a number of time delays to the feedback signal when the feedback signal and the reference signal are miss-aligned.
摘要翻译：描述了一种用于电子设备中的时钟源同步的混合相位和时域的双环控制和调谐时钟相位对准的装置和方法。粗略校准单元产生多个输出信号，输出信号之间具有多个固定相间隔。固定相位间隔中的至少一个等于完成360度，其除以输出信号的数量以覆盖完整360度的相位范围。连接到粗校准单元的第一精细校准单元通过耦合可编程延迟电路来延迟从粗校准单元生成的输出信号，以将反馈信号的相位调整到参考信号的相位。连接到第一精细校准单元的相位检测器用于检测参考和反馈信号之间的相位差，并输出与参考和反馈信号之间的相位差对应的指示信号。控制器控制粗略校准单元和第一精细校准单元，以根据从相位检测器产生的指示信号将反馈信号与参考信号对准。当反馈信号和参考信号错过对准时，旋转检测器通过向反馈信号添加多个时间延迟来快速调谐反馈信号和参考信号之间的相位差。

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