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1. 发明授权

US4810528A Process for producing multilayer circuit board 失效
标题翻译：多层电路板生产工艺
公开(公告)号：US4810528A
公开(公告)日：1989-03-07
申请号：US901335
申请日：1986-08-28
申请人： Kazuo Kondo , Hisaharu Shiromizu , Asao Morikawa , Tsuneyuki Sukegawa
发明人： Kazuo Kondo , Hisaharu Shiromizu , Asao Morikawa , Tsuneyuki Sukegawa
IPC分类号： C03C17/36 , H05K1/03 , H05K1/09 , H05K3/12 , H05K3/46 , B05D5/12
CPC分类号： H05K3/4667 , H05K1/092 , H05K1/0306
摘要： A process for producing a multilayer circuit board composed of crystallized glass and copper-metallized circuit patterns, which comprises:(1) providing a green sheet of a crystallizable glass powder;(2) providing a copper paste comprising copper component (copper and/or copper oxide) and a glass powder in a proportion by weight of the copper component to the glass powder 95:5 to 75:25, copper oxide being calculated on copper;(3) printing a circuit pattern of the copper paste of step (2) on the green sheet of step (1);(4) coating on the green sheet of step (3) an insulating paste to form an insulating layer except for regions assigned for through holes;(5) printing on the insulating layer of step (4) a circuit pattern of the copper paste of step (2) and filling said holes with the copper paste make a conductive connection through said holes;(6) decomposing the binders by heating the product of step (5) under an oxidizing atmosphere at 400.degree.-850.degree. C.; and(7) heating the product of step (6) at 850.degree.-1050.degree. C. under a reducing atmosphere for a period of time sufficient to reduce copper oxide, sinter the product of step (6) and crystallize said glasses.After step (5), pairs of steps (4) and (5) are repeated to make multilayer circuit boards.
摘要翻译：一种由结晶玻璃和铜金属化电路图形成的多层电路板的制造方法，其特征在于，包括：（1）提供可结晶玻璃粉末的生片; （2）将铜成分（铜和/或氧化铜）和铜成分重量比的玻璃粉末提供给玻璃粉末95:5〜75:25，铜计算的铜膏; （3）在步骤（1）的生片上印刷步骤（2）的铜浆的电路图案; （4）在步骤（3）的生片上涂覆绝缘膏，以形成除了通孔的区域之外的绝缘层; （5）在步骤（4）的绝缘层上印刷步骤（2）的铜浆的电路图案并用铜浆填充所述孔，通过所述孔形成导电连接; （6）通过在400-850℃的氧化气氛下加热步骤（5）的产物来分解粘合剂; 和（7）在还原气氛下，在850〜-1050℃下加热步骤（6）的产物一段足以减少氧化铜的时间，烧结步骤（6）的产物并使所述玻璃结晶。在步骤（5）之后，重复步骤（4）和（5），以制造多层电路板。

2. 发明授权

US4649070A Substrate for an integrated circuit 失效
标题翻译：集成电路基板
公开(公告)号：US4649070A
公开(公告)日：1987-03-10
申请号：US808565
申请日：1985-12-13
申请人： Kazuo Kondo , Tsuneyuki Sukegawa
发明人： Kazuo Kondo , Tsuneyuki Sukegawa
IPC分类号： C03C10/00 , H01L21/48 , H01L23/15 , B32B3/00 , B32B15/04
CPC分类号： C03C10/0045 , C03C10/0054 , H01L21/4807 , H01L23/15 , H01L2924/0002 , H01L2924/09701 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
摘要： A substrate for supporting an integrated circuit made of a ceramic member with a thin film of conductive metal applied to the ceramic member. The ceramic member consists essentially of a sintered ceramic material capable of forming a surface finish upon sintering, having a roughness that is less than 10 times the thickness dimension of the conductive film applied thereto. The ceramic material is either crystalline glass or a glass-coated ceramic.
摘要翻译：一种用于支撑由陶瓷构件制成的集成电路的基板，其具有施加到陶瓷构件的导电金属薄膜。陶瓷构件基本上由烧结陶瓷材料组成，其能够在烧结时形成表面光洁度，其粗糙度小于施加到其上的导电膜的厚度尺寸的10倍。陶瓷材料是结晶玻璃或玻璃涂层陶瓷。

3. 发明授权

US4943470A Ceramic substrate for electrical devices 失效
标题翻译：陶瓷基板用于电气设备
公开(公告)号：US4943470A
公开(公告)日：1990-07-24
申请号：US320796
申请日：1989-03-09
申请人： Hisaharu Shiromizu , Asao Morikawa , Tsuneyuki Sukegawa , Kazuo Kondo
发明人： Hisaharu Shiromizu , Asao Morikawa , Tsuneyuki Sukegawa , Kazuo Kondo
IPC分类号： H01L21/48 , H01L23/15
CPC分类号： H01L21/481 , H01L23/15 , H01L2224/45147 , H01L2224/48247 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/01014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/16152 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
摘要： A ceramic substrate for an electrical device such as a layered circuit or an integrated circuit formed of a crystalline glass or ceramic material having a low densifying temperature such that conductor materials and circuits can be readily formed from high conductivity metals.
摘要翻译：一种用于诸如分层电路或由具有低致密化温度的结晶玻璃或陶瓷材料形成的集成电路的电气装置的陶瓷基板，使得可以容易地由高导电性金属形成导体材料和电路。

4. 发明授权

US4801067A Method of connecting metal conductor to ceramic substrate 失效
标题翻译：将金属导体连接到陶瓷基板的方法
公开(公告)号：US4801067A
公开(公告)日：1989-01-31
申请号：US89762
申请日：1987-08-27
申请人： Kazuo Kondo , Tsuneyuki Sukegawa , Asao Morikawa
发明人： Kazuo Kondo , Tsuneyuki Sukegawa , Asao Morikawa
IPC分类号： B23K35/00 , C04B37/02 , F01M1/08 , H01L21/00 , H01L21/48 , B23K1/04 , H01R9/06 , H05K3/00
CPC分类号： H01L21/67138 , B23K35/001 , C04B37/026 , H01L21/4853 , C04B2237/123 , C04B2237/124 , C04B2237/125 , C04B2237/126 , C04B2237/343 , C04B2237/403 , C04B2237/406 , C04B2237/407 , C04B2237/708 , C04B2237/72 , C04B2237/76 , F01M2001/086 , Y10T29/49149
摘要： A method of connecting a metal conductor to a ceramic substrate including the steps of providing a terminal portion on the ceramic substrate, the ceramic substrate having a dielectric constant less than or equal to 7.0 units and a coefficient of thermal expansion of 5.times.10.sup.-6 /.degree. C. or less, forming at least one of a buffer layer and a barrier layer overlying the terminal portion of the ceramic substrate, wherein the buffer layer consists essentially of Cu and the barrier layer consists essentially of a material selected from the group consisting of Ni, Pd, and Pt, and brazing a metal conductor to the terminal portion of the ceramic substrate through the at least one of the buffer layer and the barrier layer with an Ag-based brazing filler material.
摘要翻译：一种将金属导体连接到陶瓷基板的方法，包括以下步骤：在陶瓷基板上设置端子部分，陶瓷基板的介电常数小于或等于7.0单位，热膨胀系数为5×10 -6 /℃ 形成覆盖陶瓷衬底的端部的缓冲层和阻挡层中的至少一个，其中缓冲层基本上由Cu组成，阻挡层基本上由选自Ni ，Pd和Pt，并且通过所述缓冲层和所述阻挡层中的所述至少一个，使用Ag系钎焊料将金属导体钎焊到所述陶瓷基板的所述端子部。

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