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1. 发明授权

US5829030A System for performing cache flush transactions from interconnected processor modules to paired memory modules 失效
标题翻译：用于从互连的处理器模块到配对的存储器模块执行缓存刷新事务的系统
公开(公告)号：US5829030A
公开(公告)日：1998-10-27
申请号：US992757
申请日：1997-12-17
申请人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
发明人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
IPC分类号： G06F11/00 , G06F11/14 , G06F12/08 , G11C29/00 , G06F12/12
CPC分类号： G11C29/74 , G06F11/1407 , G06F12/0804 , G06F12/0891 , G06F11/00
摘要： A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.
摘要翻译：一种高速执行高速缓存清除操作并具有实时特性的容错计算机。处理器模块301配备有高速缓冲存储器，使得高速缓冲存储器内的更新的高速缓存块的入口地址被存储在堆栈中。当由于定时器等而导致的恢复点设置条件被满足时，高速缓冲存储器仅针对堆叠中的输入地址进行。存储器模块303具有在相同的存储物理空间中翻倍的布置，并且配备有用于临时存储所传送的高速缓存块的缓冲存储器，从而高速缓存块被同时传送到一对缓冲存储器。

2. 发明授权

US5749091A Cache controller with index stack for coherency fault tolerance 失效
标题翻译：具有索引堆栈的缓存控制器，用于一致性容错
公开(公告)号：US5749091A
公开(公告)日：1998-05-05
申请号：US355093
申请日：1994-12-13
申请人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
发明人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
IPC分类号： G06F11/00 , G06F11/14 , G06F11/16 , G06F12/08 , G11C29/00 , G06F12/12
CPC分类号： G11C29/74 , G06F11/1407 , G06F12/0804 , G06F12/0891 , G06F11/00
摘要： A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.
摘要翻译：一种高速执行高速缓存清除操作并具有实时特性的容错计算机。处理器模块301配备有高速缓冲存储器，使得高速缓冲存储器内的更新的高速缓存块的入口地址被存储在堆栈中。当由于定时器等而导致的恢复点设置条件被满足时，高速缓冲存储器仅针对堆叠中的输入地址进行。存储器模块303具有在相同的存储物理空间中翻倍的布置，并且配备有用于临时存储所传送的高速缓存块的缓冲存储器，从而高速缓存块被同时传送到一对缓冲存储器。

3. 发明授权

US5577199A Majority circuit, a controller and a majority LSI 失效
标题翻译：大多数电路，控制器和大多数LSI
公开(公告)号：US5577199A
公开(公告)日：1996-11-19
申请号：US243362
申请日：1994-05-16
申请人： Takashi Tanabe , Toshihisa Kamemaru , Mamoru Katoh , Tsugihiko Ohno , Toyohito Hatashita , Kaoru Abe
发明人： Takashi Tanabe , Toshihisa Kamemaru , Mamoru Katoh , Tsugihiko Ohno , Toyohito Hatashita , Kaoru Abe
IPC分类号： G06F11/10 , G06F11/16 , G06F11/18 , G06F11/267 , H03K19/23 , G06F11/00
CPC分类号： G06F11/185 , G06F11/187 , H03K19/23 , G06F11/1044 , G06F11/2215
摘要： This invention provides a majority circuit, connecting a plurality of processing units. The majority circuit can detect a single error or multiple errors, and sets the majority output signal to an ineffective level when multiple errors are detected. The majority circuit includes comparators, each comparing two outputs of three processing units, and the error detector recognizes the error status and outputs the single error signal and the multiple error signal accordingly. The majority circuit also includes a selector, which selects the output of a normal processing unit, when the normal processing unit can be specified based on the comparison result. The selector changes the output to a predetermined level, when the normal processing unit cannot be specified.
摘要翻译：本发明提供了连接多个处理单元的多数电路。大多数电路可以检测单个错误或多个错误，并且当检测到多个错误时将多数输出信号设置为无效级别。多数电路包括比较器，每个比较器比较三个处理单元的两个输出，误差检测器识别误差状态，并相应地输出单个误差信号和多个误差信号。大多数电路还包括选择器，当选择正常处理单元时，可以根据比较结果指定正常处理单元的输出。当不能指定正常处理单元时，选择器将输出改变为预定的水平。

4. 发明授权

US5481670A Method and apparatus for backup in a multi-memory device 失效
标题翻译：在多存储设备中备份的方法和装置
公开(公告)号：US5481670A
公开(公告)日：1996-01-02
申请号：US98806
申请日：1993-07-28
申请人： Toyohito Hatashita , Motoharu Taura , Toshihiko Shimizu , Hiroshi Umeoka
发明人： Toyohito Hatashita , Motoharu Taura , Toshihiko Shimizu , Hiroshi Umeoka
IPC分类号： G06F11/16 , G06F12/16 , G11C29/00
CPC分类号： G11C29/74
摘要： A multi-memory apparatus, configured only with identical memory units with access to the common system bus, provides secure data identity in the event of various errors by using synchronous as well as parallel operation. A memory unit in a multi-memory apparatus includes a refresh request circuit, a bus control circuit, a bus-response circuit as well as a control circuit. A master refresh request circuit issues a memory-refresh request by using the bus clock and a backup refresh request circuit issues a memory-refresh request by a trigger from the master memory. A master bus control circuit responds to the system bus and a backup bus control circuit prohibits the unit from responding. A master bus-response control circuit allows the bus control circuit to respond to the system bus and changes mode between memory units from master/backup to backup/master in the event of an error detected in the master memory unit.
摘要翻译：一种多存储器装置，其配置仅具有访问公共系统总线的相同存储器单元，通过使用同步和并行操作在各种错误的情况下提供安全的数据标识。多存储装置中的存储单元包括刷新请求电路，总线控制电路，总线响应电路以及控制电路。主刷新请求电路通过使用总线时钟发出存储器刷新请求，并且备份刷新请求电路通过来自主存储器的触发来发出存储器刷新请求。主总线控制电路响应系统总线，备用总线控制电路禁止单元响应。主总线响应控制电路允许总线控制电路在主存储器单元中检测到错误的情况下响应于系统总线并且在主/备份到备份/主机之间的存储器单元之间改变模式。

5. 发明授权

US06070232A Cache controller fault tolerant computer and data transfer system setting recovery points 失效
标题翻译：缓存控制器容错计算机和数据传输系统设置恢复点
公开(公告)号：US06070232A
公开(公告)日：2000-05-30
申请号：US948430
申请日：1997-10-10
申请人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
发明人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
IPC分类号： G06F11/00 , G06F11/14 , G06F11/16 , G06F12/08 , G11C29/00
CPC分类号： G11C29/74 , G06F11/1407 , G06F12/0804 , G06F12/0891 , G06F11/00
摘要： A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.
摘要翻译：一种高速执行高速缓存清除操作并具有实时特性的容错计算机。处理器模块配备有高速缓冲存储器，使得高速缓冲存储器内的更新的高速缓存块的入口地址被存储在堆栈中。当由于定时器等而导致的恢复点设置条件被满足时，高速缓冲存储器仅针对堆叠中的输入地址进行。存储器模块具有在相同存储物理空间中翻倍的布置，并且配备有用于临时存储所传送的高速缓存块的缓冲存储器，使得高速缓存块被同时传送到一对缓冲存储器。

6. 发明授权

US5812757A Processing board, a computer, and a fault recovery method for the computer 失效
标题翻译：处理板，计算机和计算机的故障恢复方法
公开(公告)号：US5812757A
公开(公告)日：1998-09-22
申请号：US675951
申请日：1996-07-05
申请人： Hiromu Okamoto , Takashi Tanabe , Kaoru Abe , Tsugihiko Ohno , Toyohito Hatashita , Toshihisa Kamemaru , Norihisa Kaneda , Mamoru Katoh , Masakazu Soga
发明人： Hiromu Okamoto , Takashi Tanabe , Kaoru Abe , Tsugihiko Ohno , Toyohito Hatashita , Toshihisa Kamemaru , Norihisa Kaneda , Mamoru Katoh , Masakazu Soga
IPC分类号： G06F11/16 , G06F11/18
CPC分类号： G06F11/181 , G06F11/1658 , G06F11/18 , G06F11/185 , G06F11/187 , G06F11/2007
摘要： A fault recovery process of a computer is provided for removing a fault from the system as soon as possible, minimizing the secondary fault and improving the availability of the system. In a reliable computer, which includes a system bus, a main memory connected to the system bus, and at least one processing board connected to the system bus, at least one processing board executes the same instructions by n (n>=3) processing units having cache memories respectively. When one of the processing units of the processing board becomes faulty, the other processing units continue executing the processes, which are being executed by the faulty processing board, and then, the processes to be registered in the faulty processing board, are succeeded by other processing boards.
摘要翻译：提供了一种计算机的故障恢复过程，用于尽快从系统中消除故障，最大限度地减少二次故障并提高系统的可用性。在包括系统总线，连接到系统总线的主存储器和连接到系统总线的至少一个处理板的可靠计算机中，至少一个处理板通过n（n> = 3）处理执行相同的指令具有缓存存储器的单元。当处理板的处理单元之一发生故障时，其他处理单元继续执行正在由故障处理板执行的处理，然后在故障处理板中登记的处理由其他加工板。

7. 发明申请

US20080284938A1 IMAGE DISPLAY APPARATUS 审中-公开
标题翻译：图像显示设备
公开(公告)号：US20080284938A1
公开(公告)日：2008-11-20
申请号：US12122076
申请日：2008-05-16
申请人： Koji Ichikawa , Toyohito Hatashita
发明人： Koji Ichikawa , Toyohito Hatashita
IPC分类号： G02F1/1333
CPC分类号： G02F1/133608 , G02B6/0083 , G02F1/133604 , G02F1/133615 , G02F2001/133612
摘要： The present invention relates to image display apparatuses that use a backlight source. An object of the invention is to provide an image display apparatus including an extra-length absorbing portion that improves the degree of flexibility in routing a lamp cable, which is a power supply path to a light source, and having a high degree of flexibility regarding the position for placing the power supply source. An image display apparatus of the present invention includes an image display panel, a backlight source of the image display panel, a lamp cable which is a power supply path to the light source, and an extra-length absorbing portion that absorbs an extra length of the lamp cable. The extra-length absorbing portion includes a protrusion disposed on a back surface or a side surface of the image display apparatus.
摘要翻译：本发明涉及使用背光源的图像显示装置。本发明的目的是提供一种图像显示装置，其包括超长度吸收部分，其提高了作为光源的电源路径的灯电缆的布线灵活性，并且具有关于放置电源的位置。本发明的图像显示装置包括图像显示面板，图像显示面板的背光源，作为到光源的电源路径的灯电缆，以及吸收额外长度的超长吸收部灯电缆。超长度吸收部包括设置在图像显示装置的背面或侧面的突起。

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