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    • 3. 发明授权
    • System for punctually sending and receiving serial data and a method for sending and receiving the serial data
    • 用于准时发送和接收串行数据的系统以及发送和接收串行数据的方法
    • US07266608B2
    • 2007-09-04
    • US09764299
    • 2001-01-19
    • Hitoshi IshidaMinoru Shiga
    • Hitoshi IshidaMinoru Shiga
    • G06F15/16
    • G06F13/4282
    • This invention provides an apparatus for sending and receiving serial data without losing the real time characteristics even in case of a plurality of errors. According to this invention, an overhead of the communication can be reduced, and the time for the communication can be reduced.In a system for sending and receiving serial data between a primary station and a secondary station by sending a polling request and a refresh request through a serial transmission bus in determined time, the primary station retries a polling request and a refresh request to the secondary station which has not responded normally in the same determined time after sending the polling request and the refresh request.Further, in a system which includes the primary station for sending the polling request and the refresh request through the serial transmission bus within the determined time and a plurality of secondary stations for responding to the primary station, the primary station predetermines a response order from the secondary stations, and sends the polling request and the refresh request to the secondary stations without designating an address. Each of the secondary stations checks the predetermined order, and responds accordingly.
    • 本发明提供一种用于发送和接收串行数据而不丢失实时特性的装置,即使在多个错误的情况下。 根据本发明,可以减少通信的开销,并且可以减少通信的时间。 在通过在确定的时间内通过串行传输总线发送轮询请求和刷新请求在主站和次站之间发送和接收串行数据的系统中,主站重试轮询请求和刷新请求到次站 在发送轮询请求和刷新请求之后,在相同的确定时间内没有正常响应。 此外,在包括用于在确定的时间内通过串行传输总线发送轮询请求和刷新请求的主站以及用于响应于主站的多个次站的系统中,主站预先确定来自 次站,并且将轮询请求和刷新请求发送到次站而不指定地址。 每个次站检查预定顺序,并作出相应的响应。
    • 8. 发明授权
    • Multi-processor system with fault detection
    • 具有故障检测功能的多处理器系统
    • US5452443A
    • 1995-09-19
    • US152875
    • 1993-11-15
    • Hideo OyamadaMinoru Shiga
    • Hideo OyamadaMinoru Shiga
    • G06F11/00G06F11/16G06F11/18G06F11/22G06F11/30G06F15/16G06F15/177G06F13/00
    • G06F11/0724G06F11/0757G06F11/1641G06F11/1645G06F11/1695G06F11/0763G06F11/22
    • A bus coupling type multi-processor system is disclosed having multiple processor modules and a fault detection system. A processor module includes a first processor, a second processor, and a monitor including a timer for measuring elapsed time, a register for storing a flag indicating the operation of its own processor, and a detector for detecting a fault either in its own processor or in another processor module. A starting circuit starts the second processor one clock period later than the first processor. A comparator compares the output from the first processor with the output of the second processor to detect a fault. A flag is set by its own processor module and is reset by a signal from another processor module. When a flag set by a first processor module is not reset by a second processor module, the monitor circuit in the first processor module detects this and judges that a fault has occurred in the second processor module. When a flag in a first processor module is not set within a predetermined time, the monitor circuit in a second processor module detects this and judges that a fault has occurred in the first processor module.
    • 公开了具有多个处理器模块和故障检测系统的总线耦合型多处理器系统。 处理器模块包括第一处理器,第二处理器和监视器,其包括用于测量经过时间的定时器,用于存储指示其自己的处理器的操作的标志的寄存器,以及用于在其自己的处理器或 在另一个处理器模块中。 启动电路比第一处理器晚一个时钟周期启动第二处理器。 比较器比较来自第一处理器的输出和第二处理器的输出以检测故障。 标志由其自己的处理器模块设置,并由另一个处理器模块的信号复位。 当由第一处理器模块设置的标志不被第二处理器模块复位时,第一处理器模块中的监视器电路检测到这一点,并判断在第二处理器模块中已经发生故障。 当第一处理器模块中的标志未被设置在预定时间内时,第二处理器模块中的监视器电路检测到该信号并判断在第一处理器模块中已发生故障。