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1. 发明授权

US09078358B2 Assembly structure for injection molded substrate and for mounting component 有权
标题翻译：注塑基板和安装部件的组装结构
公开(公告)号：US09078358B2
公开(公告)日：2015-07-07
申请号：US13526015
申请日：2012-06-18
申请人： Tomoaki Toratani , Toshitaka Hara , Kyutaro Abe , Motomu Shibamura , Kyosuke Hashimoto
发明人： Tomoaki Toratani , Toshitaka Hara , Kyutaro Abe , Motomu Shibamura , Kyosuke Hashimoto
IPC分类号： H05K1/16 , H05K1/02
CPC分类号： H05K1/0263 , H05K1/0271 , H05K2201/09063 , H05K2201/09072
摘要： A substrate (1) includes conductive portions (7) formed by press working and a resin portion (11) integrally injection-molded with the conductive portions (7). The conductive portions (7) are formed from, for example, a copper alloy. The resin portion 11 is formed from, for example, PPS. A surface-mount component (3), which is an electronic surface-mount component, is mounted on the substrate (1). The surface-mount component (3) has electrodes (5) at its opposite sides, and the electrodes (5) and the respective conductive portions (7) are electrically connected by means of a solder (9). The substrate (1) has a hole (13), which functions as a stress relaxation mechanism, formed in the resin portion (11) (a portion extending therethrough) between connection portions (15) under the surface-mount component (3). The substrate (1) also has resin-exposed portions (13), which function as a stress relaxation mechanism, formed on opposite sides of the surface-mount component (3).
摘要翻译：基板（1）包括通过冲压加工形成的导电部分（7）和与导电部分（7）整体注模的树脂部分（11）。导电部（7）例如由铜合金形成。树脂部11由例如PPS形成。作为电子表面安装部件的表面安装部件（3）安装在基板（1）上。表面安装部件（3）在其相对侧具有电极（5），电极（5）和相应的导电部分（7）通过焊料（9）电连接。基板（1）具有在表面安装部件（3）下方的连接部（15）之间形成在树脂部（11）（贯穿其中的部分）上的作为应力松弛机构的孔（13）。基板（1）还具有形成在表面安装部件（3）的相对侧上的用作应力松弛机构的树脂暴露部分（13）。

2. 发明申请

US20120255767A1 ASSEMBLY STRUCTURE FOR INJECTION MOLDED SUBSTRATE AND FOR MOUNTING COMPONENT 有权
标题翻译：注射成型基板和安装部件的组装结构
公开(公告)号：US20120255767A1
公开(公告)日：2012-10-11
申请号：US13526015
申请日：2012-06-18
申请人： Tomoaki TORATANI , Toshitaka HARA , Kyutaro ABE , Motomu SHIBAMURA , Kyosuke HASHIMOTO
发明人： Tomoaki TORATANI , Toshitaka HARA , Kyutaro ABE , Motomu SHIBAMURA , Kyosuke HASHIMOTO
IPC分类号： H05K1/18
CPC分类号： H05K1/0263 , H05K1/0271 , H05K2201/09063 , H05K2201/09072
摘要： A substrate (1) includes conductive portions (7) formed by press working and a resin portion (11) integrally injection-molded with the conductive portions (7). The conductive portions (7) are formed from, for example, a copper alloy. The resin portion 11 is formed from, for example, PPS. A surface-mount component (3), which is an electronic surface-mount component, is mounted on the substrate (1). The surface-mount component (3) has electrodes (5) at its opposite sides, and the electrodes (5) and the respective conductive portions (7) are electrically connected by means of a solder (9). The substrate (1) has a hole (13), which functions as a stress relaxation mechanism, formed in the resin portion (11) (a portion extending therethrough) between connection portions (15) under the surface-mount component (3). The substrate (1) also has resin-exposed portions (13), which function as a stress relaxation mechanism, formed on opposite sides of the surface-mount component (3).
摘要翻译：基板（1）包括通过冲压加工形成的导电部分（7）和与导电部分（7）整体注模的树脂部分（11）。导电部（7）例如由铜合金形成。树脂部11由例如PPS形成。作为电子表面安装部件的表面安装部件（3）安装在基板（1）上。表面安装部件（3）在其相对侧具有电极（5），电极（5）和相应的导电部分（7）通过焊料（9）电连接。基板（1）具有在表面安装部件（3）下方的连接部（15）之间形成在树脂部（11）（贯穿其中的部分）上的作为应力松弛机构的孔（13）。基板（1）还具有形成在表面安装部件（3）的相对侧上的用作应力松弛机构的树脂暴露部分（13）。

3. 发明授权

US4129859A Raster scan type CRT display system having an image rolling function 失效
标题翻译：具有图像滚动功能的光栅扫描型CRT显示系统
公开(公告)号：US4129859A
公开(公告)日：1978-12-12
申请号：US766728
申请日：1977-02-08
申请人： Masahiro Iwamura , Nagaharu Hamada , Toshitaka Hara , Nobuo Sato
发明人： Masahiro Iwamura , Nagaharu Hamada , Toshitaka Hara , Nobuo Sato
IPC分类号： G09G5/32 , G09G5/34 , G06F3/14
CPC分类号： G09G5/343
摘要： A raster scan type CRT display system is disclosed which has a randomly accessable refresh memory. The display system comprises column and row start address registers for defining a read start address for the refresh memory, column and row address counters for counting the contents of the column and row start address registers as start positions to generate a read address of the refresh memory for display, column and row cursor registors for defining a data entry position on a CRT screen, and column and row address generators for generating an entry address for the refresh memory based on the contents of the column and row start address registers and the contents of the column and row cursor registers, whereby a rolling or shifting of the image is effected and the refresh memory can be accessed by a processor for read/write operation without the need to monitor the image rolling.
摘要翻译：公开了一种具有随机存取的刷新存储器的光栅扫描型CRT显示系统。显示系统包括用于定义刷新存储器的读起始地址的列和行起始地址寄存器，用于对列的内容进行计数的列和行地址计数器以及行起始地址寄存器作为起始位置，以生成刷新存储器的读地址用于在CRT屏幕上定义数据输入位置的显示器，列和行光标注册器，以及用于根据列和行起始地址寄存器的内容产生刷新存储器的入口地址的列和行地址生成器，列和行光标寄存器，从而影响图像的滚动或移位，并且可以由处理器访问刷新存储器以进行读/写操作，而不需要监视图像滚动。

4. 发明授权

US3947818A Bus-coupler 失效
标题翻译：总线耦合器
公开(公告)号：US3947818A
公开(公告)日：1976-03-30
申请号：US531161
申请日：1974-12-09
申请人： Yoshiki Kobayashi , Tadaaki Bandoh , Toshitaka Hara
发明人： Yoshiki Kobayashi , Tadaaki Bandoh , Toshitaka Hara
IPC分类号： G06F13/36 , G06F13/40 , H04L12/40 , H04L29/08 , H04Q9/00
CPC分类号： G06F13/4036
摘要： A bus-coupler or bus window in an information transport system for connecting a plurality of buses, to each of which a plurality of arithmetic units, a plurality of memory or storage units and a plurality of input-output units are connected separately through stations. The bus coupler includes a dead-lock control circuit for preventing a dead-lock which could possibly occur in communication between the buses.
摘要翻译：用于连接多个总线的信息传输系统中的总线耦合器或总线窗口，其中多个运算单元，多个存储器或存储单元以及多个输入 - 输出单元通过站单独连接。总线耦合器包括用于防止在总线之间的通信中可能发生的死锁的死锁控制电路。

5. 发明授权

US5490143A Multiplex transmission method and a synchronizing method in multiplex transmission 失效
标题翻译：复用传输中的多路复用传输方法和同步方法
公开(公告)号：US5490143A
公开(公告)日：1996-02-06
申请号：US240492
申请日：1994-05-10
申请人： Toshitaka Hara , Yutaka Matsuda , Kyosuke Hashimoto , Hiroo Moriue , Yoshikazu Nobutoki , Hiroaki Sakamoto , Koji Terayama , Hideki Nakazono
发明人： Toshitaka Hara , Yutaka Matsuda , Kyosuke Hashimoto , Hiroo Moriue , Yoshikazu Nobutoki , Hiroaki Sakamoto , Koji Terayama , Hideki Nakazono
IPC分类号： H04L12/413 , H04J3/06
CPC分类号： H04J3/0605 , H04L12/4135
摘要： When a message is transmitted, frame by frame, from any one (10) of a plurality of multiplex nodes to a common multiplex bus (MB) to which the multiplex nodes are connected, each of the multiplex nodes (20 and 30) determines that transmission of a frame therefrom is allowed when it detects a transmission permission signal (b, b') added to the frame after detection of and idle state of the multiplex bus, and starts transmitting a message data frame. This makes it possible to properly implement priority-based control according to the priority levels of the data frames irrespectively of variations in the reference clocks of the multiplex nodes. Further, receiving multiplex nodes perform frame synchronization at the rise of a special code (a) of a start code (SOM) of a message data frame, and then perform re-synchronization at the rise of a special bit pattern (b") which includes a passive bit and a dominant bit. This prevents synchronization from being deviated and bit errors resulting from deviated synchronization, thus leading to higher reliability of multiplex transmission.
摘要翻译：当从多个多路复用节点中的任何一个（10）到多路复用节点连接的公共多路复用总线（MB）逐帧传输消息时，多路复用节点（20和30）中的每一个确定当检测到多路复用总线的检测和空闲状态之后检测到添加到帧中的发送许可信号（b，b'）时，允许发送帧，并开始发送消息数据帧。这使得可以根据数据帧的优先级来适当地实现基于优先级的控制，而与多路复用节点的参考时钟的变化无关。此外，接收多路复用节点在消息数据帧的起始码（SOM）的特殊码（a）的上升处执行帧同步，然后在特殊位模式（b“）的上升执行重新同步，其中包括无源位和占位。这防止了同步偏离和由偏差同步引起的位错误，从而导致更高的多路传输可靠性。

6. 发明授权

US4237543A Microprocessor controlled display system 失效
标题翻译：微处理器控制显示系统
公开(公告)号：US4237543A
公开(公告)日：1980-12-02
申请号：US938954
申请日：1978-09-01
申请人： Yoji Nishio , Toshitaka Hara , Nagaharu Hamada
发明人： Yoji Nishio , Toshitaka Hara , Nagaharu Hamada
IPC分类号： G09G5/22 , G06F3/14 , G06F13/18 , G09G1/16 , G09G5/00
CPC分类号： G09G5/001 , G06F13/18 , G09G5/399 , G09G2320/0252 , G09G2360/126
摘要： A display system for displaying information in response to an input video signal comprises a data control unit including a microprocessor and a microprogram memory for storing a program for the microprocessor, a refresh memory unit connected to the data control unit through an address bus and a data bus, and a video control unit for accessing display data stored in the refresh memory unit by a timing control unit to produce a video signal. The refresh memory unit comprises memories sectioned by byte, an I/O controller which receives a read/write control signal to indicate whether the access by the data control unit is read access or write access and an access memory specifying signal to indicate whether it is a one-byte memory access or a two-byte memory access to produce an I/O control signal, and a memory controller responsive to the I/O control signal to control data access to the two byte memories.
摘要翻译：用于响应于输入视频信号显示信息的显示系统包括数据控制单元，其包括微处理器和用于存储微处理器程序的微程序存储器，通过地址总线和数据连接到数据控制单元的刷新存储器单元总线和视频控制单元，用于通过定时控制单元访问存储在刷新存储单元中的显示数据，以产生视频信号。刷新存储器单元包括以字节为单位的存储器，I / O控制器，其接收读/写控制信号以指示数据控制单元的访问是读访问还是写访问，以及访问存储器指定信号以指示是否是 1字节存储器访问或2字节存储器访问以产生I / O控制信号，以及响应于I / O控制信号来控制对两个字节存储器的数据访问的存储器控制器。

7. 发明授权

US4231032A Variable accuracy trend graph display apparatus 失效
标题翻译：可变精度趋势图显示装置
公开(公告)号：US4231032A
公开(公告)日：1980-10-28
申请号：US940367
申请日：1978-09-07
申请人： Toshitaka Hara , Nagaharu Hamada
发明人： Toshitaka Hara , Nagaharu Hamada
IPC分类号： G01R13/40 , G09G1/00 , G09G1/16 , G09G5/36 , G06F3/14
CPC分类号： G09G1/162 , G01R13/408
摘要： A graph display apparatus using a CRT display unit of raster scanning type for displaying a graph with a high accuracy, that is, a high resolution. The apparatus comprises a raster counter for counting the number of rasters to identify the raster number of the scanning lines presently scanning the display screen of the CRT display unit, and a plurality of graph display units for displaying a graph with a standard accuracy. Each graph display unit comprises a memory having a capacity corresponding to the number of time points obtained by dividing the time axis extending in the scanning direction of the raster on the display screen by the number n of data plotting for storing the raster numbers corresponding to the levels of the quantities to be displayed at the individual time points, and a comparator comparing the output of the raster counter with the output of the memory read out sequentially in timing relation with the individual time points for providing a coincidence detection signal only when coincidence is reached between the output of the counter and the output of the memory at a time point. The display signal outputs of these graph display units are combined to display a graph with a desired resolution which is for example two or four times the standard resolution. To this end, a variable accuracy circuit is associated with each of the graph display units to receive the output of the associated graph display unit thereby providing a display signal output at the timing of scanning specific dots among a plurality of dots corresponding to one time point. The outputs of the variable accuracy circuits are applied to an OR circuit which applies an output signal representing the logical sum of these inputs to the CRT display unit.
摘要翻译：使用光栅扫描型的CRT显示单元的图形显示装置，用于高精度地显示图形，即高分辨率。该装置包括：光栅计数器，用于对目前扫描CRT显示单元的显示屏幕的扫描行的光栅数进行计数，以及用于以标准精度显示图形的多个图形显示单元。每个图形显示单元包括一个存储器，该存储器具有对应于通过将显示屏幕上的光栅的扫描方向上延伸的时间轴除以通过数字绘图的数量n获得的时间点的数量，用于存储对应于在各个时间点显示的量的电平，以及比较器，其将光栅计数器的输出与存储器的输出顺序地按照与各个时间点相关的时间关系读取，以仅在符合时才提供符合检测信号在时间点之间到达计数器的输出和存储器的输出之间。这些图形显示单元的显示信号输出被组合以显示具有例如标准分辨率的两倍或四倍的期望分辨率的图形。为此，可变精度电路与每个图形显示单元相关联，以接收相关联的图形显示单元的输出，从而在对应于一个时间点的多个点中扫描特定点的定时提供显示信号输出。可变精度电路的输出被施加到OR电路，其将表示这些输入的逻辑和的输出信号施加到CRT显示单元。

8. 发明授权

US4200869A Data display control system with plural refresh memories 失效
标题翻译：具有多个刷新存储器的数据显示控制系统
公开(公告)号：US4200869A
公开(公告)日：1980-04-29
申请号：US877803
申请日：1978-02-14
申请人： Norio Murayama , Yukitaka Hayashi , Nagaharu Hamada , Toshitaka Hara
发明人： Norio Murayama , Yukitaka Hayashi , Nagaharu Hamada , Toshitaka Hara
IPC分类号： G06F17/21 , G09G5/22 , G09G5/32 , G09G5/34 , G09G5/397 , G09G5/399 , G06F3/14
CPC分类号： G09G5/343 , G09G5/222
摘要： A data display control system for displaying respective data memorized in a plurality of refresh memories which is operable in various display modes including a selective picture display, a superimposed picture display and a shifting picture display. Individual data memorized in respective refresh memories contain each a display control bit adapted to determine whether or not the individual data are to be displayed on the screen. The data display control system reads out from the respective refresh memories a data information to be picture-displayed and only when the contents of a display control bit contained in the data information designate a display, it converts this data information into a video signal for a picture display. The contents of the display control bit are changeable for individual data.
摘要翻译：一种数据显示控制系统，用于显示存储在多个刷新存储器中的各种数据，该多个刷新存储器可在包括选择性图像显示，叠加图像显示和移位图像显示在内的各种显示模式下操作。存储在各个刷新存储器中的各个数据包含每个显示控制位，用于确定是否在屏幕上显示各个数据。数据显示控制系统从相应的刷新存储器读出要被图像显示的数据信息，并且只有当数据信息中包含的显示控制位的内容指定显示时，才将该数据信息转换为视频信号图片显示。显示控制位的内容可以针对各个数据进行更改。

9. 发明授权

US4156904A Computer systems having a common memory shared between a central processor and a CRT display 失效
标题翻译：具有在中央处理器和CRT显示器之间共享的公共存储器的计算机系统
公开(公告)号：US4156904A
公开(公告)日：1979-05-29
申请号：US827112
申请日：1977-08-23
申请人： Yasuo Minowa , Toshitaka Hara , Nagaharu Hamada
发明人： Yasuo Minowa , Toshitaka Hara , Nagaharu Hamada
IPC分类号： G06F3/153 , G06F13/18 , G06F13/28 , G09G1/16 , G09G5/00 , G06F13/00 , G06F3/14
CPC分类号： G09G5/001 , G06F13/18 , G06F13/28 , G06F3/153 , G09G2320/0247 , G09G2360/18
摘要： A computer system comprises a central processor unit, a single memory apparatus and an external processor unit which is adapted to read out N bytes of data in each period of T.sub.o. The number n of data remaining to be processed after a time elapse T.sub.1 (T.sub.1
摘要翻译：计算机系统包括中央处理器单元，单个存储器装置和外部处理器单元，其适于在To的每个周期中读出N字节的数据。在从时段To开始经过T1（T1

10. 发明申请

US20120267152A1 SUBSTRATE AND METHOD OF MANUFACTURING SUBSTRATE 审中-公开
标题翻译：基板和制造基板的方法
公开(公告)号：US20120267152A1
公开(公告)日：2012-10-25
申请号：US13540068
申请日：2012-07-02
申请人： Toshitaka HARA , Tomoaki TORATANI , Kyutaro ABE , Koichi MAENO , Motomu SHIBAMURA
发明人： Toshitaka HARA , Tomoaki TORATANI , Kyutaro ABE , Koichi MAENO , Motomu SHIBAMURA
IPC分类号： H05K1/02 , H05K3/00
CPC分类号： B29C45/14065 , B29C45/14467 , B29C45/14639 , B29C2045/14122 , B29C2045/1454 , H02M3/00 , H05K1/0263 , H05K1/165 , H05K3/0014 , H05K3/202 , H05K2201/09118 , H05K2203/0182 , Y10T29/49158
摘要： A substrate usable for such as DC-DC converters, which has no defects such as openings therein but is more compact and easy to be manufactured and a method of manufacturing the same is provided. First, circuit materials are cut off by pressing and bended to be formed in desired shapes. Next, the circuit materials are joined or placed in predetermined positions to form a circuit conductor 15. Junction is performed by welding. Next, the circuit conductor 15 is installed on the mold 19. The mold 19 is for injection molding of resin 9 and has a predetermined cavity therein. The circuit conductor 15 is fixed to the mold 19, for example by a pin of a prescribed position. In such a condition, resin is injected into a mold. The substrate 1 is formed by the injection of resin to a surface and between layers of the circuit conductor.
摘要翻译：可用于诸如DC-DC转换器的基板，其没有诸如其中的开口的缺陷，但是更紧凑并且易于制造，并且提供了其制造方法。首先，通过按压而弯曲形成所需形状的电路材料。接下来，将电路材料接合或放置在预定位置以形成电路导体15.结通过焊接进行。接下来，电路导体15安装在模具19上。模具19用于树脂9的注射成型，并且其中具有预定的空腔。电路导体15例如通过规定位置的销固定在模具19上。在这种情况下，将树脂注入模具中。基板1通过将树脂注入到电路导体的表面和层之间而形成。

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