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    • 2. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07772853B2
    • 2010-08-10
    • US12128909
    • 2008-05-29
    • Toshifumi Shimizu
    • Toshifumi Shimizu
    • G01R31/04G01R31/02
    • H04L43/0811H01L2924/0002H01L2924/00
    • Provided is a semiconductor device determining connection status between an output terminal connected to an output buffer and an external device, the semiconductor device including a test voltage generating circuit to generate test voltage for changing voltage of the output terminal, a connection detection determining circuit to compare voltage of the output terminal with reference voltage and to determine connection status of the external device based on the comparing result, and a compensation circuit generating simulation current where leak current generated at the output buffer is reproduced in a simulatory manner and compensating voltage change of the output terminal by the simulation current.
    • 提供一种确定连接到输出缓冲器的输出端子与外部装置之间的连接状态的半导体器件,所述半导体器件包括测试电压产生电路,以产生用于改变输出端子电压的测试电压,连接检测确定电路进行比较 电压,并根据比较结果确定外部设备的连接状态;以及补偿电路,产生模拟电流,模拟电流以模拟方式再现输出缓冲器产生的漏电流,并补偿电压变化 输出端通过仿真电流。
    • 9. 发明授权
    • Load open state detection using H-bridge driving circuit
    • 使用H桥驱动电路加载开路状态检测
    • US5592097A
    • 1997-01-07
    • US441199
    • 1995-05-15
    • Toshifumi ShimizuYumiko IwanamiKazuhiro Mori
    • Toshifumi ShimizuYumiko IwanamiKazuhiro Mori
    • G01R31/02G01R31/42
    • G01R31/42G01R31/025
    • A load open state detection circuit includes a driver having X and Y terminals between which an inductive load is connected and which receive drive signals, a first transistor whose base is connected to the X terminal and whose collector is connected to a terminal supplied with a predetermined voltage, a second transistor whose base is connected to the Y terminal and whose collector is connected to the terminal supplied with a predetermined voltage and third and fourth transistors having bases thereof connected to input terminals supplied with respective drive signals. A fifth transistor has a base connected to the base of the first transistor, a collector connected to a resistor which is in turn connected to the collector of the first transistor, and an emitter connected to a second resistor which is connected to the emitter of the first transistor. A sixth transistor is provided, having a base connected to the base of the fourth transistor and a collector and emitter connected through respective resistors to the collector and emitter of the fourth transistor, respectively. A logic gate circuit receives voltages of the collectors of the fifth and sixth transistors to determine whether or not a load current flows between X and Y terminals to thereby detect whether the load is in a normal or an open state.
    • 负载打开状态检测电路包括具有X和Y端子的驱动器,在该端子之间连接有感性负载并且接收驱动信号的第一晶体管,其基极连接到X端子并且其集电极连接到提供有预定的 电压,第二晶体管的基极连接到Y端子,其集电极连接到提供有预定电压的端子,第三和第四晶体管的基极连接到提供有相应驱动信号的输入端。 第五晶体管具有连接到第一晶体管的基极的基极,连接到电阻器的集电极,电阻器又连接到第一晶体管的集电极,以及连接到第二电阻器的发射极,第二电阻器连接到第一晶体管的发射极 第一晶体管。 提供第六晶体管,其具有连接到第四晶体管的基极的基极和通过相应电阻器分别连接到第四晶体管的集电极和发射极的集电极和发射极。 逻辑门电路接收第五和第六晶体管的集电极的电压,以确定负载电流是否在X和Y端子之间流动,从而检测负载是正常还是打开状态。