会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Mobile telephone
    • 具有将具有扇区数据结构的半导体存储器应用于其存储器系统的技术的移动电话
    • US06771979B2
    • 2004-08-03
    • US09836374
    • 2001-04-18
    • Tomoya Fukuzumi
    • Tomoya Fukuzumi
    • H04M100
    • G06F12/0802G06F3/0607G06F3/064G06F3/0679G06F2212/2022G11C2207/16
    • A mobile telephone (52) comprises a flash memory (3) having a sector data structure. A flash memory (3) has a sector data structure and stores user data (UD) and a firmware (FW) in a sector unit. A user data buffer (4A) and a firmware buffer (4B) are random accessible memories. The buffers (4A) and (4B) store the user data (UD) and firmware (FW) transferred from the memory (3) together with recognition numbers thereof, respectively. As a result of retrieval in the buffer (4B) which is carried out by a CPU (1), when the firmware (FW) required for the execution of an operation input by a user is not present in the buffer (4B), the CPU (1) controls a sequencer (2) to transfer the necessary firmware (FW) from the memory (3) to the buffer (4B). The CPU (1) executes the operational contents by utilizing the firmware (FW) in the buffer (4B). The CPU (1) also utilizes the user data (UD) in the same manner as the firmware (FW).
    • 移动电话(52)包括具有扇区数据结构的快闪存储器(3)。 闪速存储器(3)具有扇区数据结构,并将用户数据(UD)和固件(FW)存储在扇区单元中。 用户数据缓冲器(4A)和固件缓冲器(4B)是随机存取存储器。 缓冲器(4A)和(4B)分别存储从存储器(3)传送的用户数据(UD)和固件(FW)及其识别号码。 作为在由CPU(1)执行的缓冲器(4B)中检索的结果,当在缓冲器(4B)中不存在执行用户输入的操作所需的固件(FW)时, CPU(1)控制定序器(2)将必要的固件(FW)从存储器(3)传送到缓冲器(4B)。 CPU(1)通过利用缓冲器(4B)中的固件(FW)来执行操作内容。 CPU(1)也以与固件(FW)相同的方式使用用户数据(UD)。
    • 4. 发明授权
    • Memory card
    • 存储卡
    • US5761144A
    • 1998-06-02
    • US627132
    • 1996-04-03
    • Tomoya Fukuzumi
    • Tomoya Fukuzumi
    • G06F12/14G06F3/08G06F21/00G06F21/06G06K17/00G06K19/07G07F7/10
    • G07F7/1008G06F21/79G06K19/0723G06Q20/341G07F7/082
    • A memory card includes a volatile memory device, and a power supply supplying an electric voltage to the memory device while the memory card is connected to a host. A timer is started when the memory card is connected to the system. A current detector detects a current flow between a pair of terminals connected to a host. A power supply controller provided between the memory device and the power supply opens repetitively when the current detector does not detect a prescribed current flow before the timer completes a prescribed timing cycle. Thus, the memory card can be accessed only when it is connected to a host having a security function in correspondence to the memory card, while it clears the data stored therein when it is connected to a host which does not correspond to the memory card. Preferably, the current detector is activated by an active signal received from a host. The memory card may also include a timer activated when the memory card is connected to the host or when an active signal is supplied from the host. The memory card also includes at least one pair of terminals connected to corresponding terminals of the host, a current detector detecting current flow between the terminals, and a power supply controller for opening repetitively between the memory device and the power supply when the current detector does not detect a prescribed current flow before the timer completes a prescribed timing cycle.
    • 存储卡包括易失性存储装置,以及在存储卡连接到主机时向存储装置提供电压的电源。 当存储卡连接到系统时,启动定时器。 电流检测器检测连接到主机的一对终端之间的电流。 当定时器完成规定的定时周期之前,当电流检测器未检测到规定的电流时,设置在存储器件和电源之间的电源控制器重复地打开。 因此,只有当存储卡连接到具有与存储卡相对应的安全功能的主机时,才可以访问存储卡,同时当存储卡连接到与存储卡不对应的主机时,可以将其存储在其中。 优选地,电流检测器由从主机接收的有效信号激活。 存储卡还可以包括当存储卡连接到主机时或当从主机提供活动信号时激活的定时器。 存储卡还包​​括连接到主机的相应端子的至少一对端子,检测端子之间的电流的电流检测器以及当电流检测器执行时在存储器件和电源之间重复打开的电源控制器 在定时器完成规定的定时周期之前未检测到规定的电流。
    • 5. 发明授权
    • Multi-chip IC memory device with a single command controller and signal
clock generator
    • 具有单个指令控制器和信号时钟发生器的多芯片IC存储器件
    • US5910917A
    • 1999-06-08
    • US139658
    • 1998-08-25
    • Tomoya Fukuzumi
    • Tomoya Fukuzumi
    • G11C16/02G11C7/10G11C7/22G11C8/12G11C16/04G11C7/00
    • G11C7/22G11C7/10G11C8/12
    • An IC memory device reduces the time required to complete operations for reading, writing, or erasing data continuously from the same sector address in plural memory chips by accomplishing said operations with a single command and sector address input operation. This IC memory device comprises a data control unit, a command control unit, and a serial clock signal generator. The data control unit handles command and data I/O operations between a data bus and the memory chips. The command control unit generates and applies a chip enable signal to each corresponding memory chip based on externally supplied command data. The serial clock signal generator generates an internal serial clock signal supplied to each memory chip based on an externally supplied serial clock signal. Data can thus be read, written, or erased continuously at the same sector address in plural memory chips with the operating command and sector address being input only once.
    • 通过用单个命令和扇区地址输入操作完成所述操作,IC存储器件减少完成从多个存储器芯片中相同扇区地址连续读取,写入或擦除数据所需的时间。 该IC存储器件包括数据控制单元,命令控制单元和串行时钟信号发生器。 数据控制单元处理数据总线和存储器芯片之间的命令和数据I / O操作。 命令控制单元根据外部提供的命令数据生成并对每个对应的存储器芯片施加芯片使能信号。 串行时钟信号发生器基于外部提供的串行时钟信号产生提供给每个存储器芯片的内部串行时钟信号。 因此,可以在多个存储器芯片中的相同扇区地址连续地读取,写入或擦除数据,其中操作命令和扇区地址仅被输入一次。
    • 6. 发明授权
    • Storage device
    • 储存设备
    • US06363009B1
    • 2002-03-26
    • US09677878
    • 2000-10-03
    • Tomoya Fukuzumi
    • Tomoya Fukuzumi
    • G11C1604
    • G06F12/0246G06F2212/7202G06F2212/7207G11C8/12G11C11/5621G11C16/08G11C2211/5641
    • A two-valued flash memory (2) and multivalued flash memories (31-33) are mixed in a flash memory group (200) so that management data and user data are stored into the two-valued flash memory (2) and the multivalued flash memories (31-33), respectively. A CPU (4) operates based on universal physical addresses. On the other hand, a two-valued/multivalued selector (7), and a two-valued flash sequencer (6a) and a multivalued flash sequencer (6b) in a flash interface (6) operate based on individual physical addresses so that the management data and the user data to be transmitted/received are divided among the two-valued flash memory (2) and the multivalued flash memories (31-33). This increases storage capacity and transfer rate of a flash storage medium.
    • 二值闪速存储器(2)和多值闪速存储器(31-33)在闪存组(200)中混合,使得管理数据和用户数据被存储到二值闪存(2)和多值 闪存(31-33)。 CPU(4)基于通用物理地址进行操作。 另一方面,闪存接口(6)中的二值/多值选择器(7)和二值闪光定序器(6a)和多值闪光定序器(6b)基于各个物理地址进行操作, 管理数据和要发送/接收的用户数据在二值闪速存储器(2)和多值闪速存储器(31-33)之间分配。 这增加了闪存存储介质的存储容量和传送速率。
    • 10. 发明授权
    • Security system apparatus for a memory card and memory card employed
therefor
    • 用于存储卡和用于其的存储卡的安全系统装置
    • US5845066A
    • 1998-12-01
    • US707377
    • 1996-09-04
    • Tomoya Fukuzumi
    • Tomoya Fukuzumi
    • G06F12/14G06F21/00G06F21/24G06K17/00G06K19/073
    • G06F21/78G06F12/1466
    • In a security system apparatus for a memory card used in an information processing apparatus, the memory card has an enciphering control data storing section which stores enciphering control data from which a predetermined password can be obtained by decoding, a main memory section, storing the data from the information processing apparatus, a comparison password storing section which stores a reference password, a password comparison section which compares the reference password with the password from the information processing apparatus, and an access control section for controlling access to main memory section. The information processing apparatus is provided with a data decoding section for decoding the enciphering control data. The information processing apparatus outputs the decoded password to the password comparison section and the access control section prohibits the access to the main memory section unless passwords coincide with each other as a result of the comparison by the password comparison section.
    • 在用于信息处理装置的存储卡的安全系统装置中,存储卡具有加密控制数据存储部,该加密控制数据存储部存储通过解码得到预定密码的加密控制数据,主存储部存储数据 从信息处理装置,存储参考密码的比较密码存储部分,将来自信息处理装置的参考密码与密码进行比较的密码比较部分,以及用于控制对主存储部分的访问的访问控制部分。 信息处理装置设置有用于对加密控制数据进行解码的数据解码部分。 信息处理装置将解码的密码输出到密码比较部分,并且访问控制部分禁止访问主存储部分,除非密码比较部分的比较结果,密码彼此一致。