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1. 发明授权

US08706996B2 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US08706996B2
公开(公告)日：2014-04-22
申请号：US12844800
申请日：2010-07-27
申请人： Yuki Kondoh , Tohru Nojiri
发明人： Yuki Kondoh , Tohru Nojiri
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30101 , G06F9/3824 , G06F12/1458
摘要： The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains. For example, in case that the domain manager performs data transfer between domains in the enhanced access mode, a read access from the domain manager is disguised as a read access from a first domain, and a write access from the domain manager is disguised as a write access from a second domain.
摘要翻译：数据处理器可以形成包括并行运行的两个或多个操作系统的组合的系统，其在操作系统之间实现更高的数据传输速率，并且在不损害系统可靠性的情况下提高系统性能。在系统中，域之间的数据传输以增强的访问模式以及访问模式进行，其中来自具有域的控制的域管理员的访问被从域管理器处理为一个。通过将来自域管理器的访问视为来自在域上工作的软件程序的访问的访问模式，增强访问模式被设置为CPU规模，并且域管理器的软件程序在域名例如，如果域管理器在增强访问模式下执行域之间的数据传输，则来自域管理器的读取访问被伪装成来自第一域的读取访问，并且来自域管理器的写入访问被伪装为从第二个域写入访问。

2. 发明申请

US20110131577A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20110131577A1
公开(公告)日：2011-06-02
申请号：US12958687
申请日：2010-12-02
申请人： Tohru NOJIRI , Yuki Kondoh
发明人： Tohru NOJIRI , Yuki Kondoh
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/4411 , G06F9/45541 , G06F13/102 , G06F13/105
摘要： This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.
摘要翻译：本发明旨在减少管理程序开销。在本文公开的数据处理器中，当设备驱动程序要求访问控制寄存器以激活专用受控外围设备的处理时，直接处理访问，而不用管理程序进行处理。当从专用的受控外围设备产生中断时，由管理外围设备的操作系统的设备驱动程序直接发起一个过程，而不会由管理程序进行处理。通过在处理器中实现这种控制方式，可以在不经管理程序处理的情况下执行外围设备控制。从而减轻虚拟机管理程序开销。

3. 发明授权

US6041399A VLIW system with predicated instruction execution for individual instruction fields 失效
标题翻译：具有针对各个指令字段执行预定指令的VLIW系统
公开(公告)号：US6041399A
公开(公告)日：2000-03-21
申请号：US884667
申请日：1997-06-27
申请人： Koichi Terada , Keiji Kojima , Yoshifumi Fujikawa , Tohru Nojiri , Kiyokazu Nishioka
发明人： Koichi Terada , Keiji Kojima , Yoshifumi Fujikawa , Tohru Nojiri , Kiyokazu Nishioka
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3824
摘要： In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of operations is made among a plurality of processing units executing in parallel the operations, transfer of the register file is frequently generated among the processing units, resulting in insufficient effect of the high speed operations. In view of solving this problem, the predicate registers are provided and moreover a means for broadcasting the update data of the predicate register to all processing units is also provided. Thereby, operations for obtaining branching condition and numerical value can be realized in different processing units and the number of steps of the processing program can be reduced. In addition, since high speed transfer between the processing units of the data register having a wider bit width is no longer required and thereby the mounting area can be reduced and high speed processing unit can be realized.
摘要翻译：在构成具有VLIW类型处理单元的特征的处理单元和流水线类型处理单元的特性的情况下，由于在并行执行操作的多个处理单元中进行操作结果的参考，因此，在处理单元之间经常生成寄存器文件，导致高速操作的效果不足。为了解决这个问题，提供了谓词寄存器，并且还提供了用于向所有处理单元广播谓词寄存器的更新数据的装置。因此，可以在不同的处理单元中实现获得分支条件和数值的操作，并且可以减少处理程序的步数。此外，由于不再需要具有较宽位宽的数据寄存器的处理单元之间的高速传输，从而可以减小安装面积，并可实现高速处理单元。

4. 发明授权

US5870618A Processor and data processor 失效
标题翻译：处理器和数据处理器
公开(公告)号：US5870618A
公开(公告)日：1999-02-09
申请号：US681180
申请日：1996-07-22
申请人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
发明人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
IPC分类号： G06F9/305 , G06F9/30 , G06F9/302 , G06F9/34 , G06F9/38 , G06F9/26
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30101
摘要： An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the cost of the hardware being increased so much and the first long register 12 and the second long register 13 having a bit width which is two times of the bit width of the register file and the long register update device 14 for updating the data of the second long register 13 partially are installed between the register file 2 and the pixel calculator 11. When the long register update pixel calculation instruction is stored in the instruction register 31, the long register update device 14 connects a part of the data of the second long register 13 and a part of data read from the register file 2 and sends them to the pixel calculator 11 and the second long register 13 via the selector 15. The pixel calculator 11 executes calculation between the data of the first long register 12 and the data given from the selector 15.
摘要翻译：本发明的目的是提供一种处理器，其可以在高速的数据长度大于寄存器文件的数据长度的数据长度的数据之间进行计算，而不会增加硬件的成本，并且第一长寄存器12和具有位宽度为寄存器堆的位宽度的二倍的第二长寄存器13和用于更新第二长寄存器13的数据的长寄存器更新装置14部分地安装在寄存器堆2和像素计算器当长寄存器更新像素计算指令存储在指令寄存器31中时，长寄存器更新装置14连接第二长寄存器13的数据的一部分和从寄存器文件2读取的数据的一部分，并将它们发送经由选择器15传送到像素计算器11和第二长寄存器13.像素计算器11执行第一长寄存器12的数据和数据gi之间的计算从选择器15发出。

5. 发明授权

US5815696A Pipeline processor including interrupt control system for accurately perform interrupt processing even applied to VLIW and delay branch instruction in delay slot 失效
标题翻译：管道处理器包括中断控制系统，用于准确执行中断处理，甚至应用于VLIW，并延迟延迟槽中的分支指令
公开(公告)号：US5815696A
公开(公告)日：1998-09-29
申请号：US888789
申请日：1997-07-07
申请人： Kazuhiko Tanaka , Tohru Nojiri , Keiji Kojima , Kiyokazu Nishioka , Yoshiki Kurokawa
发明人： Kazuhiko Tanaka , Tohru Nojiri , Keiji Kojima , Kiyokazu Nishioka , Yoshiki Kurokawa
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48
CPC分类号： G06F9/327 , G06F9/30149 , G06F9/3804
摘要： There is provided an instruction supply unit 20 for generating addresses for each instruction when an interrupt occurs, from an interrupted instruction until an instruction to be executed later by the number of instructions contained in a delay slot of the instruction an interrupt control unit 50 for storing each address thus generated, and an instruction executing unit 30 for successively reading out each of the stored addresses from the address of the interrupted address after the interrupt processing is completed. The instruction executing unit 30 executes a branch instruction to the address which is first read out. Thereafter, with respect to the addresses which are read out secondly and subsequently, if the address is the branch destination address of the branch instruction, the instruction executing unit 30 executes the branch instruction to the address, and if the address is not the branch destination address, it executes an NOP instruction. Accordingly, even when the instruction length is not fixed, the interrupt can be accurately processed.
摘要翻译：提供了一个指令提供单元20，用于当中断发生时，从中断指令到稍后执行的指令的指令生成指令的延迟时隙中的指令数量，用于存储每个指令的地址，中断控制单元50用于存储每个地址如此生成，以及指令执行单元30，用于在完成中断处理之后，从中断地址的地址中连续地读出每个存储的地址。指令执行单元30对首先被读出的地址执行分支指令。此后，对于第二次读出的地址，随后，如果地址是分支指令的分支目的地地址，则指令执行单元30对该地址执行分支指令，如果地址不是分支目的地地址，它执行一个NOP指令。因此，即使指令长度不固定，也能够正确地进行中断处理。

6. 发明授权

US5307502A Data processing system having multiple register management for call and return operations 失效
标题翻译：数据处理系统具有多个用于呼叫和返回操作的寄存器管理
公开(公告)号：US5307502A
公开(公告)日：1994-04-26
申请号：US945930
申请日：1992-09-17
申请人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
发明人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4425 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating main memory is provided in the same instruction.
摘要翻译：在配备有大量寄存器的计算机系统中，其存取时间比主存储器短得多;寄存器指定地址部分，其中具有寄存器区域的寄存器地址的区域寄存器的分配作为其值，以及在每个指令中提供了表示寄存器区域内的相对寄存器地址的寄存器位移值的分配，使得即使当物理寄存器增加时，也可以减少对任务切换等等的寄存器的保存和恢复以达到程序运行处理速度提高。此外，在同一指令中提供了用于指定主存储器的地址部分。

7. 发明申请

US20110055528A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20110055528A1
公开(公告)日：2011-03-03
申请号：US12844800
申请日：2010-07-27
申请人： Yuki KONDOH , Tohru Nojiri
发明人： Yuki KONDOH , Tohru Nojiri
IPC分类号： G06F9/318
CPC分类号： G06F9/30101 , G06F9/3824 , G06F12/1458
摘要： The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains. For example, in case that the domain manager performs data transfer between domains in the enhanced access mode, a read access from the domain manager is disguised as a read access from a first domain, and a write access from the domain manager is disguised as a write access from a second domain.
摘要翻译：数据处理器可以形成包括并行运行的两个或多个操作系统的组合的系统，其在操作系统之间实现更高的数据传输速率，并且在不损害系统可靠性的情况下提高系统性能。在系统中，域之间的数据传输以增强的访问模式以及访问模式进行，其中来自具有域的控制的域管理员的访问被从域管理器处理为一个。通过将来自域管理器的访问视为来自在域上工作的软件程序的访问的访问模式，增强访问模式被设置为CPU规模，并且域管理器的软件程序在域名例如，如果域管理器在增强访问模式下执行域之间的数据传输，则来自域管理器的读取访问被伪装成来自第一域的读取访问，并且来自域管理器的写入访问被伪装为从第二个域写入访问。

8. 发明申请

US20090109875A1 Network Topology Management System, Management Apparatus, Management Method, Management Program, and Storage Media That Records Management Program 审中-公开
标题翻译：网络拓扑管理系统，管理设备，管理方法，管理程序和记录管理程序的存储介质
公开(公告)号：US20090109875A1
公开(公告)日：2009-04-30
申请号：US12328592
申请日：2008-12-04
申请人： Yasunori KANEDA , Tohru NOJIRI
发明人： Yasunori KANEDA , Tohru NOJIRI
IPC分类号： H04L12/28
CPC分类号： H04L61/2038 , H04L29/12254 , H04L29/12839 , H04L41/12 , H04L61/106 , H04L61/6022
摘要： A network topology management system includes information processing units, storage units, connection units that control connection switching between the information processing units and the storage units, a management unit that manages a network topology consisting of the information processing units, the storage units and the connection units, and an emulator connected to the connection units and to the management unit the network. The emulator comprises a conversion section that converts first equipment identification information that identifies the information processing units or the storage units into second equipment identification information that is recognizable by the management unit to identify the information processing units or the storage units, and a transmitting section that sends the second equipment identification information to the management unit. The management device has a control section that manages the network topology based on the second equipment identification information.
摘要翻译：网络拓扑管理系统包括控制信息处理单元和存储单元之间的连接切换的信息处理单元，存储单元，连接单元，管理由信息处理单元，存储单元和连接组成的网络拓扑的管理单元单元，以及连接到连接单元和管理单元的仿真器。仿真器包括转换部分，其将识别信息处理单元或存储单元的第一设备识别信息转换成可由管理单元识别以识别信息处理单元或存储单元的第二设备识别信息，以及发送部分，将第二设备识别信息发送到管理单元。管理装置具有基于第二设备识别信息管理网络拓扑的控制部。

9. 发明授权

US5179685A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US5179685A
公开(公告)日：1993-01-12
申请号：US372696
申请日：1989-06-28
申请人： Tohru Nojiri
发明人： Tohru Nojiri
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/5016 , G06F9/462
摘要： An information processing apparatus for managing a storage such as a register file divided into a plurality of register banks. A register bank pointer is provided for each register bank in the register file so as to link the register bank to another optional register bank. The activation records for each of a plurality of tasks are allocated to the corresponding register banks in the register file. The necessary number of register banks for the allocation of the activation records for each task are linked together. The number of register banks linked together or released from the linking is changed with the increase and decrease of the number of activation records to be allocated for each task.
摘要翻译：一种用于管理分成多个寄存器组的诸如寄存器文件的存储的信息处理装置。为寄存器文件中的每个寄存器组提供寄存器组指针，以将寄存器组链接到另一个可选的寄存器组。多个任务中的每一个的激活记录被分配给寄存器文件中的对应的寄存器组。为每个任务分配激活记录的必要数量的寄存器组链接在一起。链接在一起或从链接释放的寄存器组的数量随着为每个任务分配的激活记录的数量的增加和减少而改变。

10. 发明申请

US20100274880A1 Network Topology Management System, Management Apparatus, Management Method, Management Program, and Storage Media That Records Management Program 审中-公开
标题翻译：网络拓扑管理系统，管理设备，管理方法，管理程序和记录管理程序的存储介质
公开(公告)号：US20100274880A1
公开(公告)日：2010-10-28
申请号：US12813366
申请日：2010-06-10
申请人： Yasunori KANEDA , Tohru NOJIRI
发明人： Yasunori KANEDA , Tohru NOJIRI
IPC分类号： G06F15/173
CPC分类号： H04L61/2038 , H04L29/12254 , H04L29/12839 , H04L41/12 , H04L61/106 , H04L61/6022
摘要： A network topology management system includes information processing units, storage units, connection units that control connection switching between the information processing units and the storage units, a management unit that manages a network topology consisting of the information processing units, the storage units and the connection units, and an emulator connected to the connection units and to the management unit the network. The emulator comprises a conversion section that converts first equipment identification information that identifies the information processing units or the storage units into second equipment identification information that is recognizable by the management unit to identify the information processing units or the storage units, and a transmitting section that sends the second equipment identification information to the management unit. The management device has a control section that manages the network topology based on the second equipment identification information.
摘要翻译：网络拓扑管理系统包括控制信息处理单元和存储单元之间的连接切换的信息处理单元，存储单元，连接单元，管理由信息处理单元，存储单元和连接组成的网络拓扑的管理单元单元，以及连接到连接单元和管理单元的仿真器。仿真器包括转换部分，其将识别信息处理单元或存储单元的第一设备识别信息转换成可由管理单元识别以识别信息处理单元或存储单元的第二设备识别信息，以及发送部分，将第二设备识别信息发送到管理单元。管理装置具有基于第二设备识别信息管理网络拓扑的控制部。

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