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    • 2. 发明授权
    • Memory request interlock
    • 内存请求互锁
    • US06810470B1
    • 2004-10-26
    • US09638550
    • 2000-08-14
    • John R. WisemanGlen Timothy McDonnell
    • John R. WisemanGlen Timothy McDonnell
    • G06F1214
    • G06F13/1631
    • A memory controller for use in a computer system. The controller has a buffer having an input configured to receive read and write requests. Each request has an associated memory address. For a selected received request, prior received requests out of a set of the received requests are determined. For each determined prior received request, that request's memory address is compared to the selected request's memory address to see if they match. If a match exists, the selected request is prevented from being memory executed.
    • 一种用于计算机系统的存储器控​​制器。 控制器具有缓冲器,其具有被配置为接收读取和写入请求的输入。 每个请求都有一个关联的内存地址。 对于所选择的接收到的请求,确定一组接收到的请求中的先前接收到的请求。 对于每个确定的先前接收到的请求,将该请求的存储器地址与所选择的请求的存储器地址进行比较,以查看它们是否匹配。 如果存在匹配,则禁止所选择的请求被执行。