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    • 1. 发明授权
    • ESD protection during GMR head fabrication
    • GMR头制造期间的ESD保护
    • US06470566B2
    • 2002-10-29
    • US09754139
    • 2001-01-03
    • Richard HsiaoEdward Hin Pong LeeTimothy J. MoranJoseph Francis SmythHoward Gordon Zolla
    • Richard HsiaoEdward Hin Pong LeeTimothy J. MoranJoseph Francis SmythHoward Gordon Zolla
    • G11B5127
    • G11B5/3903G11B5/3163G11B5/3173G11B5/40Y10T29/49032Y10T29/49043
    • To protect the MR read head element from ESD damage during wafer level manufacturing, a lead from the MR element is electrically connected to one or both of the read head element shields during manufacturing. In a preferred embodiment of the present invention, the electrical connection is fabricated in the kerf area between adjacent magnetic heads as they are fabricated upon a wafer substrate. Thereafter, when the magnetic heads are separated by saw cutting through the kerf areas, the electrical connections are thereby removed, such that the MR element electrical leads and the shields are electrically isolated. In an alternative embodiment, one or more of the shields, as well as the MR element leads can also be electrically connected to the substrate upon which the magnetic head is fabricated. In further alternative embodiments, the electrical connection between one or more of the shields and the MR element electrical lead can be fabricated within the magnetic head area, rather than in the kerf area, and a suitable resistance is fabricated into the interconnecting circuit. In this embodiment, the electrical interconnection between the MR element electrical lead and one or more of the shields has a pre-designed electrical resistance and it remains in the magnetic head following fabrication.
    • 为了在晶片级制造期间保护MR读取头元件免受ESD损坏,来自MR元件的引线在制造期间电连接到读头元件屏蔽中的一个或两个。 在本发明的优选实施例中,当在晶片衬底上制造时,在相邻磁头之间的切口区域中制造电连接。 此后,当通过锯切通过切口区域分离磁头时,由此去除电连接,使得MR元件电引线和屏蔽件电隔离。 在替代实施例中,一个或多个屏蔽件以及MR元件引线也可以电连接到其上制造磁头的基板。 在另外的替代实施例中,一个或多个屏蔽件和MR元件电引线之间的电连接可以制造在磁头区域内,而不是在切口区域中,并且在互连电路中制造合适的电阻。 在该实施例中,MR元件电引线与一个或多个屏蔽之间的电互连具有预先设计的电阻,并且在制造之后它保持在磁头中。
    • 9. 发明授权
    • Device and method of reducing ESD damage in thin film read heads which enables measurement of gap resistances and method of making
    • 减薄薄膜读取头中的ESD损伤的装置和方法,能够测量间隙电阻和制作方法
    • US06678127B2
    • 2004-01-13
    • US09753804
    • 2001-01-02
    • Richard HsiaoJames D. JarrattEmo Hilbrand KlaassenIan Robson McFadyenTimothy J. Moran
    • Richard HsiaoJames D. JarrattEmo Hilbrand KlaassenIan Robson McFadyenTimothy J. Moran
    • G11B540
    • B82Y10/00G11B5/33G11B5/3967G11B5/40G11B5/455G11B33/10G11B2005/0013Y10T29/49032Y10T29/49036Y10T29/49039Y10T29/49043Y10T29/49044Y10T29/49071Y10T29/49073Y10T29/49078
    • A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together. A test instrument is then employed for determining the combined parallel resistance of the resistors RS1 and RS2 by having a first side of the test instrument connected to the first node and the second side connected to each of the first and second shield layers. In the second embodiment a third resistor RS3 is connected between the second node and one of the shield layers, such as the second shield layer. The test instrument can determine the resistances of the first and second gap layers separately by being connected between the first node and the first shield layer for the resistance of the first gap layer or between the first node and the second shield layer for the resistance of the second gap layer.
    • 第一读取间隙层在第一屏蔽层和读取头的第一和第二引线层中的一个之间具有电阻RG1,并且第二读取间隙层在第二屏蔽层和第一和第二引线之间的电阻RG2 读头的引导层。 通过第一节点和第一和第二屏蔽层中的每一个之间的多个电阻器提供连接,其中多个电阻器至少包括第一和第二电阻器RS1和RS2,并且第一节点连接到第一和第二屏蔽层中的所述第一和第二屏蔽层 第二铅层。 第二节点位于第一和第二电阻器RS1和RS2之间。 运算放大器具有分别连接到第一和第二节点的第一和第二输入,以跨过第一电阻器RS1并且具有连接到第一节点的输出,用于将第一和第二节点维持在共同的电压电位。 在第一实施例中,第一和第二屏蔽层被短路在一起。 然后通过使测试仪器的第一侧连接到第一节点并且第二侧连接到第一和第二屏蔽层中的每一个,然后采用测试仪器来确定电阻器RS1和RS2的组合并联电阻。 在第二实施例中,第三电阻器RS3连接在第二节点和其中一个屏蔽层之间,例如第二屏蔽层。 测试仪器可以通过连接在第一节点和第一屏蔽层之间来分别确定第一和第二间隙层的电阻,用于第一间隙层的电阻或第一节点和第二屏蔽层之间的电阻, 第二间隙层。
    • 10. 发明授权
    • Method for reducing magnetic head write gap curvature of a plated write gap
    • 降低电镀写入间隙的磁头写入间隙曲率的方法
    • US06574854B1
    • 2003-06-10
    • US09605168
    • 2000-06-27
    • Timothy J. Moran
    • Timothy J. Moran
    • G11B5127
    • G11B5/3116G11B5/23G11B5/232G11B5/3163Y10T29/49043Y10T29/49044Y10T29/49046Y10T29/49048
    • A method for forming a magnetic head to solve the curved electrodeposited write gap layer problem by initially fabricating the write gap layer to be wider than the intended final P2 pole tip width. Ion milling the sides of the P2 pole tip structure is then performed to remove the curved outer portions of the write gap layer and to thereby fabricate a P2 pole tip having the desired pole tip width. Specifically, following the electrodepositing of the write gap layer and P2 pole tip thereon, an ion milling step is conducted to remove material from the sidewalls of the P2 pole tip including the write gap layer. The ion milling step is preferably conducted utilizing a broad beam ion milling device that is directed to the surface of the substrate upon which the magnetic heads are being fabricated. Preferably, the ion beam is directed at an angle of approximately 70° away from normal to the substrate surface such that milling of the head side surfaces is efficiently accomplished. Following the ion milling step the curved edges of the write gap layer are removed and the P2 pole tip width is narrowed to its desired dimension. Thereafter, further well known fabrication steps are conducted to complete the fabrication of the magnetic head.
    • 通过最初制造写入间隙层比预期的最终P2极尖宽度宽的方法,形成磁头来解决弯曲的电沉积写间隙层问题的方法。 然后对P2极端部结构的侧面进行离子铣削,以去除写入间隙层的弯曲外部部分,从而制造具有所需磁极尖端宽度的P2极尖端。 具体地说,在写入间隙层和P2极端部电沉积之后,进行离子研磨步骤以从包括写入间隙层的P2极端子的侧壁去除材料。 离子研磨步骤优选使用被引导到正在制造磁头的基底的表面的宽束离子研磨装置进行。 优选地,离子束以与基板表面法线成大约70°的角度被引导,使得头侧表面的铣削被有效地实现。 在离子铣削步骤之后,去除写间隙层的弯曲边缘,并将P2极尖端宽度变窄到其所需的尺寸。 此后,进行进一步公知的制造步骤以完成磁头的制造。