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1. 发明授权

US08340239B2 Decoder and method for adaptively generating a clock window 有权
标题翻译：用于自适应地生成时钟窗口的解码器和方法
公开(公告)号：US08340239B2
公开(公告)日：2012-12-25
申请号：US12651983
申请日：2010-01-04
申请人： Tien-Ju Tsai
发明人： Tien-Ju Tsai
IPC分类号： H04L7/02
CPC分类号： H04N7/0352
摘要： A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.
摘要翻译：解码器和相关方法自适应地生成时钟窗口。检测水平同步信号的下降沿，确定实际帧码与预定帧码之间的时间差。然后，基于下降沿和时间差自适应地确定时钟窗口的开始和结束，使得可以在生成的时钟窗口内执行通过接收的时钟输入信号的符号定时恢复。

2. 发明授权

US08281208B2 Receiver with capability of correcting error 有权
标题翻译：接收机具有校正误差的能力
公开(公告)号：US08281208B2
公开(公告)日：2012-10-02
申请号：US12791801
申请日：2010-06-01
申请人： Tien-Ju Tsai
发明人： Tien-Ju Tsai
IPC分类号： H03M13/00
CPC分类号： H04L1/0065 , H03M13/19 , H03M13/2933 , H03M13/6577 , H04L1/0045
摘要： A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.
摘要翻译：公开了一种具有校正误差能力的接收机。软切片器产生量化数据和相关联的软数据。具有错误恢复的解码器产生解码的量化数据和软序列，并且能够校正量化数据的一位。具有码校正器的串并行（S / P）转换器产生并行数据，并且能够校正两位解扰数据位。

3. 发明申请

US20120099600A1 TRANSCEIVER HAVING HEAC AND ETHERNET CONNECTIONS 审中-公开
标题翻译：具有HEAC和以太网连接的收发器
公开(公告)号：US20120099600A1
公开(公告)日：2012-04-26
申请号：US12908772
申请日：2010-10-20
申请人： TIEN-JU TSAI
发明人： TIEN-JU TSAI
IPC分类号： H04L12/56
CPC分类号： H04L12/413
摘要： A transceiver having HEAC and Ethernet connections is disclosed. An active hybrid & common-mode bias (AHCB) unit facilitates the transmission of differential transmission signals and the reception of first differential reception signals. An Ethernet line gate controllably configures the pairing among first and second differential Ethernet signals, the differential transmission signals and second differential reception signals. An Ethernet physical-layer (PHY) transceiving unit receives both or one of the first and second differential reception signals and the differential transmission signals, followed by processing the reception signals at a physical layer.
摘要翻译：公开了一种具有HEAC和以太网连接的收发器。有源混合和共模偏置（AHCB）单元有助于差分传输信号的传输和第一差分接收信号的接收。以太网线路栅极可控地配置第一和第二差分以太网信号之间的配对，差分传输信号和第二差分接收信号。以太网物理层（PHY）收发单元接收第一和第二差分接收信号和差分传输信号中的一个或其中之一，随后在物理层处理接收信号。

4. 发明授权

US08019453B2 Decimator and decimating method for multi-channel audio 有权
标题翻译：多通道音频的抽取和抽取方法
公开(公告)号：US08019453B2
公开(公告)日：2011-09-13
申请号：US11682462
申请日：2007-03-06
申请人： Tien Ju Tsai , Chao Wei Huang
发明人： Tien Ju Tsai , Chao Wei Huang
IPC分类号： G06F17/00
CPC分类号： H04H40/45 , H04H20/34
摘要： A decimator is used to process a multi-channel audio signal, and includes a memory, a controller and a processing unit. The processing unit is used to decimate each input audio component of a multi-channel audio signal to generate corresponding multi-channel operational data. The controller is used to control read and write actions for each audio component of the multi-channel audio signal and the multi-channel operational data into or from the memory. The memory provides a digital signal process for decimation together with the processing unit. The input of the multi-channel audio and the output of the multi-channel operational data are performed through time division. Compared with conventional decimator circuits, the decimator circuit of the present invention reduces the cost and the power consumption of the hardware circuitry.
摘要翻译：抽取器用于处理多声道音频信号，并且包括存储器，控制器和处理单元。处理单元用于抽取多声道音频信号的每个输入音频分量以产生相应的多声道操作数据。该控制器用于控制多通道音频信号的每个音频分量和多通道操作数据进入存储器或从存储器读取和写入动作。存储器提供与处理单元一起抽取的数字信号处理。通过时分执行多声道音频的输入和多声道操作数据的输出。与传统抽取器电路相比，本发明的抽取器电路降低了硬件电路的成本和功耗。

5. 发明申请

US20110187937A1 METHOD FOR FREQUENCY COMPENSATION AND RELATED APPARATUS 审中-公开
标题翻译：频率补偿方法及相关装置
公开(公告)号：US20110187937A1
公开(公告)日：2011-08-04
申请号：US12699060
申请日：2010-02-03
申请人： Shiang-Lun Kao , Tien-Ju Tsai
发明人： Shiang-Lun Kao , Tien-Ju Tsai
IPC分类号： H04N5/44 , H04B1/18
CPC分类号： H04B1/18 , H04N5/44 , H04N21/8106
摘要： A method for frequency compensation includes the following steps: detecting and checking if a desired frequency falls within a first detectable frequency range delimited by an initial frequency and a first specific frequency; and when the desired frequency exceeds the first detectable frequency range, utilizing a first frequency compensation step with a step size greater than a size of the first detectable frequency range for shifting the initial frequency to a first adjusted frequency beyond the first specific frequency in a first direction.
摘要翻译：一种用于频率补偿的方法包括以下步骤：检测并检查所需频率是否落在由初始频率和第一特定频率限定的第一可检测频率范围内; 并且当期望频率超过第一可检测频率范围时，利用具有大于第一可检测频率范围的步长的步长的第一频率补偿步骤，用于将第一频率的初始频率移动到超过第一特定频率的第一调整频率方向。

6. 发明授权

US07945058B2 Noise reduction system 有权
标题翻译：降噪系统
公开(公告)号：US07945058B2
公开(公告)日：2011-05-17
申请号：US11460449
申请日：2006-07-27
申请人： Kai-Ting Lee , Tien-Ju Tsai
发明人： Kai-Ting Lee , Tien-Ju Tsai
IPC分类号： H04B15/00 , H03G7/00
CPC分类号： G10L21/0364
摘要： A noise reduction system is used in a BTSC system to reduce noise of an audio signal. The noise reduction system has an audio spectral compressing unit that has a filter and a memory in the approach of the digital processing. The filter is arranged to filter an input signal according to a transfer function, a variable d, and several parameters b0/a0, a0/b0, b1/b0 and a1/a0. The memory is arranged to store the parameters.
摘要翻译：在BTSC系统中使用降噪系统来降低音频信号的噪声。降噪系统具有在数字处理方法中具有滤波器和存储器的音频频谱压缩单元。滤波器被设置为根据传递函数，变量d和几个参数b0 / a0，a0 / b0，b1 / b0和a1 / a0对输入信号进行滤波。存储器被设置为存储参数。

7. 发明申请

US20100240334A1 Broadcast Receiver and Method for Regulating the Same 有权
标题翻译：广播接收机及其调节方法
公开(公告)号：US20100240334A1
公开(公告)日：2010-09-23
申请号：US12409029
申请日：2009-03-23
申请人： Shin-Shiuan Cheng , Guo-Hau Gau , Shan-Tsung Wu , Shih-Chuan Lu , Tien-Ju Tsai
发明人： Shin-Shiuan Cheng , Guo-Hau Gau , Shan-Tsung Wu , Shih-Chuan Lu , Tien-Ju Tsai
IPC分类号： H04B1/18
CPC分类号： H03G3/3068 , H04H60/43
摘要： A broadcast receiver includes a tuner circuit and a demodulator circuit. The tuner circuit tunes a radio frequency (RF) signal to output an intermediate frequency (IF) signal. The demodulator circuit demodulates the IF signal from the tuner circuit and outputs a command signal based on the quality of the IF signal, for changing a take over point (TOP) value, preset in the tuner circuit, at which one amplitude gain control (AGC) stopping and another taking over. A method for regulating a broadcast receiver is also disclosed herein.
摘要翻译：广播接收机包括调谐器电路和解调器电路。调谐器电路调谐射频（RF）信号以输出中频（IF）信号。解调器电路解调来自调谐器电路的IF信号，并且基于IF信号的质量输出命令信号，以改变在调谐器电路中预设的接收点（TOP）值，其中一个幅度增益控制（AGC ）停止和另一个接管。本文还公开了一种用于调节广播接收机的方法。

8. 发明授权

US07656883B2 Transmission convergence sublayer circuit and operating method for asynchronous receiver 有权
标题翻译：传输汇聚子层电路和异步接收机的操作方法
公开(公告)号：US07656883B2
公开(公告)日：2010-02-02
申请号：US11858135
申请日：2007-09-20
申请人： Tien-Ju Tsai , Chih-Feng Lin
发明人： Tien-Ju Tsai , Chih-Feng Lin
IPC分类号： H04L12/54
CPC分类号： H04Q11/0478 , H04L2012/5647 , H04L2012/5653 , H04L2012/5673
摘要： A transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.
摘要翻译：传输会聚子层电路耦合在缓冲器和解帧器之间。解帧器向电路提交数据流使能信号和数据字节。数据流使能信号使能电路，使得属于数据信元的多组字节数据被接收并临时存储在字节数据流水线内。标题循环冗余校验器还接收字节数据，然后进行标题搜索。使用空闲小区标识符来确定数据小区是否是非空闲小区。当标头被找到并被确定为非空闲小区时，解扰器从字节数据流水线检索数据信元的有效载荷数据，并且在获得等于双字的数据量之后进行解扰操作。最终，双字数据以最小的延迟输出到缓冲器。

9. 发明申请

US20090262246A1 Method and apparatus for determining sound standard for input sound signal 有权
标题翻译：用于确定输入声音信号的声音标准的方法和装置
公开(公告)号：US20090262246A1
公开(公告)日：2009-10-22
申请号：US12081745
申请日：2008-04-21
申请人： Tien-Ju Tsai , Shih-Chuan Lu , Shu-Ming Liu
发明人： Tien-Ju Tsai , Shih-Chuan Lu , Shu-Ming Liu
IPC分类号： H04N5/14
CPC分类号： H04N5/60 , H04N5/46 , H04N21/4394
摘要： A method for determining a sound standard for an input sound signal includes the following steps. Firstly, the input sound signal is filtered to obtain a first filtered signal corresponding to a first frequency and a second filtered signal corresponding to a second frequency. Next, the first filtered signal is frequency-demodulated to obtain a first demodulated filtered signal, and whether the input sound signal contains a FM analog component corresponding to the first frequency is determined accordingly. Next, the second filtered signal is decoded according to a digital sound standard to obtain a bit stream. Then, the bit steam is interpreted according to the digital sound standard, and whether the input sound contains a digital component corresponding to the digital sound standard is determined accordingly. Then, whether the input sound signal matches one of known sound standards is determined based on the determined results above.
摘要翻译：用于确定输入声音信号的声音标准的方法包括以下步骤。首先，对输入声音信号进行滤波以获得对应于第一频率的第一滤波信号和对应于第二频率的第二滤波信号。接下来，对第一滤波信号进行频率解调以获得第一解调滤波信号，并且相应地确定输入声音信号是否包含与第一频率相对应的FM模拟分量。接下来，根据数字声音标准对第二滤波信号进行解码以获得比特流。然后，根据数字声音标准解释位蒸汽，并且相应地确定输入声音是否包含与数字声音标准相对应的数字分量。然后，基于上述确定的结果来确定输入声音信号是否与已知声音标准中的一个匹配。

10. 发明申请

US20130028299A1 ADAPTIVE ETHERNET TRANSCEIVER WITH JOINT DECISION FEEDBACK EQUALIZER AND TRELLIS DECODER 审中-公开
标题翻译：自适应以太网收发器与联合决策反馈均衡器和TRELLIS解码器
公开(公告)号：US20130028299A1
公开(公告)日：2013-01-31
申请号：US13191286
申请日：2011-07-26
申请人： TIEN-JU TSAI
发明人： TIEN-JU TSAI
IPC分类号： H04L5/16
CPC分类号： H04L25/03057 , H03M13/256 , H03M13/4107 , H03M13/4184 , H03M13/6331 , H04B3/23 , H04B3/32 , H04L1/0047 , H04L1/006 , H04L25/03866 , H04L25/4919 , H04L25/497 , H04L2025/03369
摘要： An adaptive Ethernet transceiver is disclosed. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal. A decoder control unit is configured to adaptively disable a portion of the joint DFE and Trellis decoder in a non-specified link speed mode.
摘要翻译：公开了一种自适应以太网收发器。联合决策反馈均衡器（DFE）和网格解码器被配置为对接收信号进行解码。解码器控制单元被配置为以非指定的链路速度模式自适应地禁用联合DFE和网格解码器的一部分。

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