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    • 2. 发明授权
    • System and a method of correcting baseline wander
    • 系统和校正基线漂移的方法
    • US08174417B2
    • 2012-05-08
    • US12901318
    • 2010-10-08
    • Chih-Feng Lin
    • Chih-Feng Lin
    • H03M1/06
    • H03M1/1019H03M1/12
    • A system and method of correcting baseline wander (BLW) are disclosed. An analog-to-digital converter (ADC) converts an analog input to a digital output, and a slicer maps the digital output to one of a plurality of predefined values. A BLW correction unit generates a BLW correction value according to a difference between an input and an output of the slicer. A correction controller generates a fine correction value and a coarse correction value according to the BLW correction value. Specifically, the fine correction value is used to correct the digital output of the ADC, and the coarse correction value is used to correct the analog input of the ADC.
    • 公开了一种校正基线漂移(BLW)的系统和方法。 模拟 - 数字转换器(ADC)将模拟输入转换为数字输出,并且限幅器将数字输出映射到多个预定义值中的一个。 BLW校正单元根据限幅器的输入和输出之间的差产生BLW校正值。 校正控制器根据BLW校正值产生精细校正值和粗略校正值。 具体来说,使用精细校正值来校正ADC的数字输出,粗校正值用于校正ADC的模拟输入。
    • 3. 发明申请
    • SYSTEM AND A METHOD OF CORRECTING BASELINE WANDER
    • 系统和校正基线的方法
    • US20120086588A1
    • 2012-04-12
    • US12901318
    • 2010-10-08
    • Chih-Feng LIN
    • Chih-Feng LIN
    • H03M1/06H03M1/12
    • H03M1/1019H03M1/12
    • A system and method of correcting baseline wander (BLW) are disclosed. An analog-to-digital converter (ADC) converts an analog input to a digital output, and a slicer maps the digital output to one of a plurality of predefined values. A BLW correction unit generates a BLW correction value according to a difference between an input and an output of the slicer. A correction controller generates a fine correction value and a coarse correction value according to the BLW correction value. Specifically, the fine correction value is used to correct the digital output of the ADC, and the coarse correction value is used to correct the analog input of the ADC.
    • 公开了一种校正基线漂移(BLW)的系统和方法。 模拟 - 数字转换器(ADC)将模拟输入转换为数字输出,并且限幅器将数字输出映射到多个预定义值中的一个。 BLW校正单元根据限幅器的输入和输出之间的差产生BLW校正值。 校正控制器根据BLW校正值产生精细校正值和粗略校正值。 具体来说,使用精细校正值来校正ADC的数字输出,粗校正值用于校正ADC的模拟输入。
    • 4. 发明授权
    • Transmission convergence sublayer circuit and operating method for asynchronous receiver
    • 传输汇聚子层电路和异步接收机的操作方法
    • US07656883B2
    • 2010-02-02
    • US11858135
    • 2007-09-20
    • Tien-Ju TsaiChih-Feng Lin
    • Tien-Ju TsaiChih-Feng Lin
    • H04L12/54
    • H04Q11/0478H04L2012/5647H04L2012/5653H04L2012/5673
    • A transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.
    • 传输会聚子层电路耦合在缓冲器和解帧器之间。 解帧器向电路提交数据流使能信号和数据字节。 数据流使能信号使能电路,使得属于数据信元的多组字节数据被接收并临时存储在字节数据流水线内。 标题循环冗余校验器还接收字节数据,然后进行标题搜索。 使用空闲小区标识符来确定数据小区是否是非空闲小区。 当标头被找到并被确定为非空闲小区时,解扰器从字节数据流水线检索数据信元的有效载荷数据,并且在获得等于双字的数据量之后进行解扰操作。 最终,双字数据以最小的延迟输出到缓冲器。
    • 10. 发明授权
    • Tolerable synchronization circuit of RDS receiver
    • RDS接收机的允许同步电路
    • US07907680B2
    • 2011-03-15
    • US11968659
    • 2008-01-03
    • Tien-Ju TsaiChih-Feng LinShih-Chuan Lu
    • Tien-Ju TsaiChih-Feng LinShih-Chuan Lu
    • H03K9/00H04L27/00
    • H04H40/18H04H2201/13
    • A Radio Data System (RDS) decoder circuit determines a subcarrier frequency utilizing only a 57 kHz RDS signal of an FM broadcast signal. The RDS decoder includes a zero-intermediate frequency (zero-IF) FM demodulator, a first mixer, a low-pass filter (LPF) unit, a shaping filter unit, a carrier recovery circuit, a digitally controlled oscillator (DCO), a symbol timing recovery circuit, an integrate and dump circuit, a slicer 280, and a differential decoder. The carrier recovery circuit includes a phase error detector and a digital loop filter (DLF). The symbol timing recovery circuit includes a zero-crossing detector, a phase detector and loop filter unit, and a counter.
    • 无线电数据系统(RDS)解码器电路仅使用FM广播信号的57kHz RDS信号来确定副载波频率。 RDS解码器包括零中频(零中频)FM解调器,第一混频器,低通滤波器(LPF)单元,整形滤波器单元,载波恢复电路,数字振荡器(DCO),数字控制振荡器 符号定时恢复电路,集成和转储电路,限幅器280和差分解码器。 载波恢复电路包括相位误差检测器和数字环路滤波器(DLF)。 符号定时恢复电路包括过零检测器,相位检测器和环路滤波器单元以及计数器。