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1. 发明授权

US08171455B2 Test sequencer and method for management and execution of sequence items 有权
标题翻译：用于管理和执行顺序项目的测序程序和方法
公开(公告)号：US08171455B2
公开(公告)日：2012-05-01
申请号：US10917869
申请日：2004-08-13
申请人： Thomas R. Fay
发明人： Thomas R. Fay
IPC分类号： G06F9/44
CPC分类号： G06F11/263
摘要： A test sequencer software application and method for management and execution of sequence items. The test sequencer software application includes a management module and an execution module. The management module has capabilities of obtaining multiple sequence items definitions, of obtaining configuration information, of creating multiple lists of ordered sequence items from the sequence items definitions, and of separately linking each list of sequence items to one of multiple sequence engines from the configuration information. The execution module includes a sequencer controller module and the multiple sequence engines. The sequence controller module activates each of the multiple sequence engines in a preselected order and each sequence engine executes the ordered sequence items in each list linked to that sequence engine.
摘要翻译：用于管理和执行顺序项目的测序程序软件应用程序和方法。测试程序软件应用程序包括管理模块和执行模块。管理模块具有获得多个序列项定义，获取配置信息，从序列项定义中创建有序序列项的多个列表以及从配置信息分别将每个序列项列表分别链接到多个序列引擎之一的能力。执行模块包括定序器控制器模块和多序列引擎。序列控制器模块以预选顺序激活多个序列引擎中的每一个，并且每个序列引擎执行链接到该序列引擎的每个列表中的有序序列项。

2. 发明授权

US4588945A High throughput circuit tester and test technique avoiding overdriving damage 失效
标题翻译：高通量电路测试仪和测试技术避免过驱动损坏
公开(公告)号：US4588945A
公开(公告)日：1986-05-13
申请号：US503465
申请日：1983-06-13
申请人： William A. Groves , Vance R. Harwood , Thomas R. Fay , Elton C. Bingham , Michael A. Teska
发明人： William A. Groves , Vance R. Harwood , Thomas R. Fay , Elton C. Bingham , Michael A. Teska
IPC分类号： G01R31/26 , G01R31/28 , G01R31/319 , G01R15/12
CPC分类号： G01R31/31915 , G01R31/28
摘要： A method and apparatus are disclosed for reducing the likelihood of damage to digital logic devices under test or located in close electrical proximity to the device under test while attempting to locate faults in circuit assemblies using digital incircuit test techniques.
摘要翻译：公开了一种方法和装置，用于降低在被测设备处的数字逻辑器件的损坏的可能性，或者使用数字电路测试技术来尝试定位电路组件中的故障时，与被测器件紧密接近。

3. 发明授权

US06324665B1 Event based fault diagnosis 失效
标题翻译：基于事件的故障诊断
公开(公告)号：US06324665B1
公开(公告)日：2001-11-27
申请号：US09185125
申请日：1998-11-03
申请人： Thomas R. Fay
发明人： Thomas R. Fay
IPC分类号： G06F1100
CPC分类号： G01R31/3193 , G01R31/31937
摘要： The present invention is a method and instrument for testing a device. The device under test (DUT) may be an electronic device, circuit, PCB, or product. The present invention compares events measured on a known good DUT with events measured on a potentially faulty DUT. Events on the DUT may be stimulated by injecting one or more input signals into the DUT. Events are observed and measured at signal nodes termed “observation nodes.” Events at the observation nodes are recorded and compiled into event lists. Event lists for a potentially faulty DUT are time aligned and compared with event lists for a known good DUT to determine whether the potentially faulty DUT is or is not actually faulty. The present invention can intelligently adapt the selection of observation nodes, on the basis of information about a DUT, to produce the most useful event lists for comparison. The present invention can backtrace through the event lists to determine the earliest or most upstream observation nodes at which the events of the potentially faulty DUT substantially differ from the events of the known good DUT. In this way, the cause of a fault can be isolated and repaired quickly. The present invention also can learn the fault cause and repair information in order to suggest the cause and needed repair when a similar event is observed on another DUT of the same type.
摘要翻译：本发明是用于测试设备的方法和仪器。被测设备（DUT）可以是电子设备，电路，PCB或产品。本发明将在已知的良好DUT上测量的事件与在潜在故障DUT上测量的事件进行比较。可以通过将一个或多个输入信号注入DUT来激发DUT上的事件。在称为“观察节点”的信号节点观察和测量事件。观察节点上的事件被记录并编译成事件列表。可能有故障的DUT的事件列表是时间对齐的，并与已知的良好DUT的事件列表进行比较，以确定潜在故障的DUT是否实际上不是有故障的。本发明可以基于有关DUT的信息智能地适应观测节点的选择，从而产生用于比较的最有用的事件列表。本发明可以通过事件列表来回溯以确定潜在故障DUT的事件与已知的良好DUT的事件基本上不同的最早或最上游观测节点。以这种方式，故障的原因可以快速隔离和修复。本发明还可以学习故障原因和修复信息，以便在同一类型的另一个DUT上观察到类似的事件时提出原因并进行必要的修复。

4. 发明授权

US07536600B2 Methods and apparatus for eliminating lower value tests for a unit under test, and for developing a plurality of different and synchronized test execution orders for testing a plurality of units under test 失效
标题翻译：用于消除被测单元的较低价值测试的方法和装置，以及开发用于测试多个待测单元的多个不同且同步的测试执行顺序
公开(公告)号：US07536600B2
公开(公告)日：2009-05-19
申请号：US11442430
申请日：2006-05-26
申请人： Thomas R. Fay , William H. Wubbena , Carl E. Benvenga
发明人： Thomas R. Fay , William H. Wubbena , Carl E. Benvenga
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： In one embodiment, test execution times are determined for a plurality of tests that are to be executed for a single unit under test (UUT). Test dependencies are also determined for the tests, as are the instruments needed to execute the tests. Then, in response to the test execution times, the test dependencies, and the instruments needed to execute the plurality of tests, a plurality of different and synchronized test execution orders for the plurality of tests are developed. Each of the test execution orders specifies a sequence of tests that is to be executed for one of a plurality of UUTs that are to be tested in parallel; and, typically, the plurality of different test execution orders will be constrained to develop different test execution orders that optimize a total time to test the plurality of UUTs, a usage cost of instruments used to test the plurality of UUTs, or both. Other embodiments are also disclosed.
摘要翻译：在一个实施例中，对于要对被测单元（UUT）执行的多个测试，确定测试执行时间。测试依赖性也是测试的依据，测试所需的仪器也是如此。然后，响应于测试执行时间，测试依赖性以及执行多个测试所需的仪器，开发出用于多个测试的多个不同且同步的测试执行顺序。每个测试执行顺序指定要对要并行测试的多个UUT中的一个执行的测试序列; 并且通常，将限制多个不同的测试执行顺序来开发不同的测试执行顺序，其优化用于测试多个UUT的总时间，用于测试多个UUT的仪器的使用成本或两者。还公开了其他实施例。

5. 发明申请

US20070294579A1 Methods and apparatus for eliminating lower value tests for a unit under test, and for developing a plurality of different and synchronized test execution orders for testing a plurality of units under test 失效
标题翻译：用于消除被测单元的较低价值测试的方法和装置，以及开发用于测试多个待测单元的多个不同且同步的测试执行顺序
公开(公告)号：US20070294579A1
公开(公告)日：2007-12-20
申请号：US11442430
申请日：2006-05-26
申请人： Thomas R. Fay , William H. Wubbena , Carl E. Benvenga
发明人： Thomas R. Fay , William H. Wubbena , Carl E. Benvenga
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： In one embodiment, test execution times are determined for a plurality of tests that are to be executed for a single unit under test (UUT). Test dependencies are also determined for the tests, as are the instruments needed to execute the tests. Then, in response to the test execution times, the test dependencies, and the instruments needed to execute the plurality of tests, a plurality of different and synchronized test execution orders for the plurality of tests are developed. Each of the test execution orders specifies a sequence of tests that is to be executed for one of a plurality of UUTs that are to be tested in parallel; and, typically, the plurality of different test execution orders will be constrained to develop different test execution orders that optimize a total time to test the plurality of UUTs, a usage cost of instruments used to test the plurality of UUTs, or both. Other embodiments are also disclosed.
摘要翻译：在一个实施例中，对于要对被测单元（UUT）执行的多个测试，确定测试执行时间。测试依赖性也是测试的依据，测试所需的仪器也是如此。然后，响应于测试执行时间，测试依赖性以及执行多个测试所需的仪器，开发出用于多个测试的多个不同且同步的测试执行顺序。每个测试执行顺序指定要对要并行测试的多个UUT中的一个执行的测试序列; 并且通常，将限制多个不同的测试执行顺序来开发不同的测试执行顺序，其优化用于测试多个UUT的总时间，用于测试多个UUT的仪器的使用成本或两者。还公开了其他实施例。

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