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    • 5. 发明授权
    • Method for the double-side polishing of a semiconductor wafer
    • 半导体晶圆的双面抛光方法
    • US08721390B2
    • 2014-05-13
    • US13041477
    • 2011-03-07
    • Juergen SchwandnerThomas BuschhardtRoland Koppert
    • Juergen SchwandnerThomas BuschhardtRoland Koppert
    • B24B1/00
    • H01L21/02024B24B37/044B24B37/08
    • A method for double-side polishing of a semiconductor wafer includes situating the semiconductor wafer in a cutout of a carrier that is disposed in a working gap between an upper polishing plate covered by a first polishing pad and a lower polishing plate covered by a second polishing pad. The first and second polishing pads each include tiled square segments that are formed by an arrangement of channels on the pads, where the square segments of the first pad are larger than the segments of the second pad. The square segments of the polishing pads include abrasives. During polishing, the carrier is guided such that a portion of the wafer temporarily projects laterally outside of the working gap. A polishing agent with a pH that is variable is supplied during polishing at a pH in a range of 11 to 12.5 during a first step and at a pH of at least 13 during a second step.
    • 一种用于半导体晶片的双面抛光的方法包括将半导体晶片置于载体的切口中,所述载体的切口位于由第一抛光垫覆盖的上抛光板和被第二抛光覆盖的下抛光板之间的工作间隙中 垫。 第一和第二抛光垫各自包括通过焊盘上的通道布置形成的平铺方形区段,其中第一焊盘的正方形段大于第二焊盘的段。 抛光垫的方形片段包括磨料。 在抛光期间,载体被引导使得晶片的一部分临时突出到工作间隙外侧。 在第一步骤期间,在pH为11至12.5的范围内,在第二步骤期间,在至少13℃的pH下,在抛光期间提供pH可变的抛光剂。
    • 6. 发明授权
    • Method for machining a semiconductor wafer on both sides in a carrier, carrier, and a semiconductor wafer produced by the method
    • 在通过该方法制造的载体,载体和半导体晶片的两侧加工半导体晶片的方法
    • US07541287B2
    • 2009-06-02
    • US11487652
    • 2006-07-17
    • Ruediger SchmolkeThomas BuschhardtGerhard HeierGuido Wenski
    • Ruediger SchmolkeThomas BuschhardtGerhard HeierGuido Wenski
    • H01L21/302
    • B24B37/28Y10S438/959
    • A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.
    • 半导体晶片被引导在载体的切口中,同时通过从前表面和背面去除材料将半导体晶片的厚度减小到目标厚度。 半导体晶片被加工直到其比载体体薄并且比用于将载体上的切口对准的嵌体更厚以保护半导体晶片。 载体的特征在于,在半导体晶片的加工整个整个持续时间内,载体主体和嵌体具有不同的厚度,载体主体比镶嵌物厚20〜70μm。 该方法提供在两侧抛光的半导体晶片,具有前表面,后表面和边缘以及前表面的局部平坦度,SFQRmax小于50nm,边缘排除R-2mm和小于nm, 基于26×8mm的场地面积,R-1mm的边缘排除。
    • 8. 发明申请
    • Method for machining a semiconductor wafer on both sides in a carrier, carrier, and a semiconductor wafer produced by the method
    • 在通过该方法制造的载体,载体和半导体晶片的两侧加工半导体晶片的方法
    • US20070021042A1
    • 2007-01-25
    • US11487652
    • 2006-07-17
    • Ruediger SchmolkeThomas BuschhardtGerhard HeierGuido Wenski
    • Ruediger SchmolkeThomas BuschhardtGerhard HeierGuido Wenski
    • B24B7/00
    • B24B37/28Y10S438/959
    • A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. The method provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than 115 nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.
    • 半导体晶片被引导在载体的切口中,同时通过从前表面和背面去除材料将半导体晶片的厚度减小到目标厚度。 半导体晶片被加工直到其比载体体薄并且比用于将载体上的切口对准的嵌体更厚以保护半导体晶片。 载体的特征在于,在半导体晶片的加工整个整个持续时间内,载体主体和嵌体具有不同的厚度,载体主体比镶嵌物厚20〜70μm。 该方法提供在两侧抛光的半导体晶片,具有前表面,后表面和边缘以及前表面的局部平坦度,SFQR 小于50nm,边缘排除 R-2mm和小于115nm,边缘排除R-1mm,基于26×8mm的位置面积。