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1. 发明授权

US07822138B2 Calculating apparatus and method for use in a maximum likelihood detector and/or decoder 有权
标题翻译：用于最大似然检测器和/或解码器的计算装置和方法
公开(公告)号：US07822138B2
公开(公告)日：2010-10-26
申请号：US10867179
申请日：2004-06-14
申请人： Oleg Zaboronski , Nicholas Atkinson , Robert Charles Jackson , Theo Drane , Andrei Vityaev
发明人： Oleg Zaboronski , Nicholas Atkinson , Robert Charles Jackson , Theo Drane , Andrei Vityaev
IPC分类号： H04L5/12 , H03M13/03
CPC分类号： H03M13/395 , H03M13/4107 , H03M13/4138
摘要： A calculator for use in a maximum likelihood detector, including: a receiver for receiving convolution encoded data which may include noise; first calculator for calculating a first component of a first path metric difference between two possible sequences of states corresponding to the convolution encoded data, the two sequences each having a length equal to a constraint length of the convolution encoded data, and the two sequences starting at a same state and ending at a same state, adapted to calculate the first component using the convolution-encoded data and using convolution encoding parameters of the convolution-encoded data, wherein the first component is independent of the two sequences; and second calculator for calculating a second component of the first path metric difference using the two sequences, wherein the second component is independent of the convolution encoded data; and using the first and second components to obtain the first path metric difference.
摘要翻译：一种用于最大似然检测器的计算器，包括：接收器，用于接收可包括噪声的卷积编码数据; 第一计算器，用于计算与卷积编码数据相对应的两个可能状态序列之间的第一路径度量差的第一分量，每个具有等于卷积编码数据的约束长度的长度的两个序列，以及从相同的状态并且以相同的状态结束，适于使用卷积编码的数据计算第一分量并使用卷积编码数据的卷积编码参数，其中第一分量独立于两个序列; 以及第二计算器，用于使用所述两个序列来计算所述第一路径量度差的第二分量，其中所述第二分量与所述卷积编码数据无关; 以及使用第一和第二分量来获得第一路径度量差。

2. 发明申请

US20050094748A1 Calculating apparatus and method for use in a maximum likelihood detector and/or decoder 有权
标题翻译：用于最大似然检测器和/或解码器的计算装置和方法
公开(公告)号：US20050094748A1
公开(公告)日：2005-05-05
申请号：US10867179
申请日：2004-06-14
申请人： Oleg Zaboronski , Nicholas Atkinson , Robert Jackson , Theo Drane , Andrei Vityaev
发明人： Oleg Zaboronski , Nicholas Atkinson , Robert Jackson , Theo Drane , Andrei Vityaev
IPC分类号： G11B20/10 , H03M13/39 , H03M13/41 , H04L1/00 , H04L25/03 , H04L25/34
CPC分类号： H03M13/395 , H03M13/4107 , H03M13/4138
摘要： A calculator for use in a maximum likelihood detector, including: a receiver for receiving convolution encoded data which may include noise; first calculator for calculating a first component of a first path metric difference between two possible sequences of states corresponding to the convolution encoded data, the two sequences each having a length equal to a constraint length of the convolution encoded data, and the two sequences starting at a same state and ending at a same state, adapted to calculate the first component using the convolution-encoded data and using convolution encoding parameters of the convolution-encoded data, wherein the first component is independent of the two sequences; and second calculator for calculating a second component of the first path metric difference using the two sequences, wherein the second component is independent of the convolution encoded data; and using the first and second components to obtain the first path metric difference.
摘要翻译：一种用于最大似然检测器的计算器，包括：接收器，用于接收可包括噪声的卷积编码数据; 第一计算器，用于计算与卷积编码数据相对应的两个可能状态序列之间的第一路径度量差的第一分量，每个具有等于卷积编码数据的约束长度的长度的两个序列，以及从相同的状态并且以相同的状态结束，适于使用卷积编码的数据计算第一分量并使用卷积编码数据的卷积编码参数，其中第一分量独立于两个序列; 以及第二计算器，用于使用所述两个序列来计算所述第一路径量度差的第二分量，其中所述第二分量与所述卷积编码数据无关; 以及使用第一和第二分量来获得第一路径度量差。

3. 发明公开

US20240220703A1 DEVICE, METHOD, AND COMPUTER-READABLE MEDIUM FOR FORMAL VERIFICATION OF A CIRCUIT DESIGN 审中-公开
公开(公告)号：US20240220703A1
公开(公告)日：2024-07-04
申请号：US18395753
申请日：2023-12-26
申请人： Samuel COWARD , Theo DRANE , George CONSTANTINIDES
发明人： Samuel COWARD , Theo DRANE , George CONSTANTINIDES
IPC分类号： G06F30/398
CPC分类号： G06F30/398
摘要： A device, method, and non-transitory computer-readable medium for generating one or more equivalent designs between a first and second circuit designs. Graphs for the first and second design are created each consisting of vertices representing operators and operands, with edges representing relationships between them. These graphs are combined into a third graph that is modified to include multiple logically equivalent designs to the original two designs by determining equivalent operators for certain vertices. From the logically equivalent designs in the third graph, a set of shared designs is extracted, consisting of vertices that are common between the equivalent designs in the first and second graphs. These shared designs may be expressed in a register transfer level (RTL) representation for validation and equivalence checking.

4. 发明公开

US20240169133A1 Apparatus, Device, Method and Computer Program for Generating an RTL Representation of a Circuit 审中-公开
公开(公告)号：US20240169133A1
公开(公告)日：2024-05-23
申请号：US18391716
申请日：2023-12-21
申请人： Theo DRANE , Samuel COWARD , George CONSTANTINIDES
发明人： Theo DRANE , Samuel COWARD , George CONSTANTINIDES
IPC分类号： G06F30/327 , G06F30/337
CPC分类号： G06F30/327 , G06F30/337
摘要： An example relates to an apparatus for generating a register transfer level (RTL) representation of a circuit, the apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to generate a graph representation of the circuit, the graph representation comprising a first set of vertices representing operators and a second set of vertices representing operands of the graph representation of the circuit. The processing circuitry is to execute the machine-readable instructions to identify one or more conditional operators, with each conditional operator defining at least two possible outcomes depending on the condition, and with each possible outcome being represented by a branch of the graph representation of the circuit. The processing circuitry is to execute the machine-readable instructions to determine, for the possible outcomes of the one or more conditional operators, a condition imposed by the respective outcome. The processing circuitry is to execute the machine-readable instructions to annotate at least a subset of the vertices of the respective branches representing the possible outcomes with the condition imposed by the corresponding outcome. The processing circuitry is to execute the machine-readable instructions to generate an RTL representation of the circuit based on the graph representation of the circuit.

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