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1. 发明授权

US06442731B2 Interactive method of optimum LSI layout including considering LSI chip size, test element groups, and alignment marks 失效
标题翻译：考虑LSI芯片尺寸，测试元件组和对准标记的最佳LSI布局的交互方法
公开(公告)号：US06442731B2
公开(公告)日：2002-08-27
申请号：US09072749
申请日：1998-05-06
申请人： Tetsuya Doi
发明人： Tetsuya Doi
IPC分类号： B06F1750
CPC分类号： G06F17/5068
摘要： A method of designing an LSI layout at a stage of making an LSI layout plan for each of a plurality of LSI chips before entering into the design of masks, which includes judging whether or not all the LSI chips can be arranged on a single wafer along with other (nonelectronic) components, based on a given LSI chip size and referring to the information on the other components. An LSI an LSI chip yield per water and/or a manufacturing cost per LSI chip are calculated, whereby an LSI layout designer can quickly and easily, within a limited LSI development term, determine how much the LSI chip size can be downsized for economical production of the LSI chip, referring to the results of the above judgment and calculation.
摘要翻译：在进入掩模设计之前，在制作LSI芯片的LSI布局图的阶段，设计LSI布局的方法，其中包括判断所有LSI芯片是否可以布置在单个晶片上与其他（非电子）组件，基于给定的LSI芯片大小，并参考其他组件的信息。计算LSI每个LSI的LSI芯片产量和/或每个LSI芯片的制造成本，由此，LSI布局设计者可以在有限的LSI开发期内快速而轻松地确定可以缩小LSI芯片尺寸以便经济生产的LSI芯片，参考上述判断和计算的结果。

2. 发明授权

US5405466A Method of manufacturing multilayer ceramic electronic component 失效
标题翻译：多层陶瓷电子元件的制造方法
公开(公告)号：US5405466A
公开(公告)日：1995-04-11
申请号：US118971
申请日：1993-09-09
申请人： Yasuyuki Naito , Tetsuya Doi , Yoshiki Hasegawa , Tadashi Morimoto , Yukio Tanaka
发明人： Yasuyuki Naito , Tetsuya Doi , Yoshiki Hasegawa , Tadashi Morimoto , Yukio Tanaka
IPC分类号： H01G4/12 , C04B37/02 , H01F41/04 , H01G4/30 , H05K1/03 , H05K3/46 , C04B37/00
CPC分类号： H01G4/30 , H01F41/043 , H05K1/0306 , H05K3/4611 , H05K3/4629
摘要： A method of manufacturing a multilayer ceramic electronic component including a step of firing a ceramic green sheet laminate having internal electrodes containing at least one of palladium and silver, and a step of firing the ceramic green sheet laminate in a furnace having an oxygen partial pressure of not more than 5% in a temperature area exceeding 50.degree. C. during a temperature rise from 400.degree. C. to 1100.degree. C.
摘要翻译：一种多层陶瓷电子部件的制造方法，其特征在于，包括具有包含钯和银中的至少一种的内部电极的陶瓷生片叠层体的工序的步骤，以及将氧分压为在400℃至1100℃的温度升高过程中，超过50℃的温度区域不超过5％。

3. 发明授权

US5219812A Dielectric ceramic composition 失效
标题翻译：介电陶瓷组合物
公开(公告)号：US5219812A
公开(公告)日：1993-06-15
申请号：US838107
申请日：1992-02-18
申请人： Tetsuya Doi , Takuya Miyagawa , Yasuyuki Naito , Tadashi Morimoto
发明人： Tetsuya Doi , Takuya Miyagawa , Yasuyuki Naito , Tadashi Morimoto
IPC分类号： C04B35/46 , C04B35/49 , H01B3/12 , H01G4/12
CPC分类号： C04B35/49 , H01B3/12 , H01G4/1245
摘要： A dielectric ceramic composition containing 0.3 to 5.0 parts by weight of an additive composed of at least one of SiO.sub.2, Li.sub.2 O and B.sub.2 O.sub.3 per 100 parts by weight of a main component expressed by the following composition formula:(1-x-y-z-t)BaTiO.sub.3 +xCaZrO.sub.3 +yMgO+zMnO+tRe.sub.2 O.sub.3,wherex.ltoreq.0.060.005.ltoreq.y.ltoreq.0.080.005.ltoreq.z.ltoreq.0.020.005.ltoreq.t.ltoreq.0.02.In the composition formula, Re indicates at least one of Y, Gd, Dy, Ho, Er and Yb.
摘要翻译：一种电介质陶瓷组合物，其含有0.3〜5.0重量份的由SiO 2，Li 2 O和B 2 O 3中的至少一种组成的添加剂，相对于以下组成式表示的主成分为100重量份：（1-xyzt）BaTiO3 + xCaZrO3 + yMgO + zMnO + tRe2O3，其中x <= 0.06 0.005

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