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1. 发明授权

US08077537B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08077537B2
公开(公告)日：2011-12-13
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
摘要翻译：提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控制器及其存储器系统。响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作，并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作在刷新目标银行。

2. 发明授权

US08004921B2 Memory device, memory controller and memory system 有权
公开(公告)号：US08004921B2
公开(公告)日：2011-08-23
申请号：US12612247
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

3. 发明授权

US07850930B2 Microreactor 失效
标题翻译：微反应器
公开(公告)号：US07850930B2
公开(公告)日：2010-12-14
申请号：US11835439
申请日：2007-08-08
申请人： Tetsuo Miyamoto , Hajime Kato , Shigenori Togashi
发明人： Tetsuo Miyamoto , Hajime Kato , Shigenori Togashi
IPC分类号： B01J19/00
CPC分类号： B01F13/0062 , B01F5/0646 , B01F5/0651 , B01F5/0653 , B01F13/0066 , B01F13/1013 , B01F13/1022 , B01J19/0093 , B01J2219/00783 , B01J2219/00889
摘要： The microreactor for mixing and discharging multiple raw material liquids is obtained by laminating: a base plate in which a raw material introducing fluid channel is formed; a raw material introducing plate; and a mixing fluid channel plate which is arranged between the base plate and the raw material introducing plate, and in which a mixing fluid channel is formed. The microreactor includes: a mixing fluid channel in the mixing fluid channel plate which is formed in the mixing fluid channel plate, and in which a flow is contracted in its width direction; and a mixing fluid channel in the base plate which is formed in the base plate, and which has a fluid channel cross-section which becomes larger in its depth direction as it goes downstream. The mixing fluid channel in the base plate communicates with the mixing fluid channel in the mixing fluid channel plate, and is connected to an outlet orifice from which to discharge the mixed liquids.
摘要翻译：用于混合和排出多种原料液体的微反应器通过层压：其中形成有原料引入流体通道的基板; 原材料导入板; 以及设置在基板和原料导入板之间的混合流体通道板，其中形成混合流体通道。微反应器包括：混合流体通道板中的混合流体通道，其形成在混合流体通道板中，并且流体在其宽度方向上收缩; 以及形成在基板中的底板中的混合流体通道，并且具有在其下游沿其深度方向变大的流体通道横截面。基板中的混合流体通道与混合流体通道板中的混合流体通道连通，并连接到排出混合液体的出口孔。

4. 发明授权

US07814294B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US07814294B2
公开(公告)日：2010-10-12
申请号：US11698286
申请日：2007-01-26
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

5. 发明申请

US20100172200A1 MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM 有权
标题翻译：存储器件，存储器控制器和存储器系统
公开(公告)号：US20100172200A1
公开(公告)日：2010-07-08
申请号：US12612247
申请日：2009-11-04
申请人： Tomohiro KAWAKUBO , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro KAWAKUBO , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
摘要翻译：提供了一种存储装置，其中已经解决了由存储装置的刷新操作引起的有效带宽的减少，存储装置的存储器控制器及其存储器系统。响应于来自存储器控制器的命令操作的存储器件具有分别具有存储器核心的多个存储体，包括存储器单元阵列和解码器，并且由存储体地址选择; 以及控制电路，其响应于后台刷新命令使由所述存储器控制器设置的刷新对象组内的存储器核心依次执行对应于由所述存储器控制器设置的刷新突发长度的次数的刷新操作，并且响应于正常操作命令，在由存储器核心执行的刷新操作期间进一步使存储器内的存储器核心在刷新对象组之外并由存储体地址选择以执行与正常操作命令相对应的正常存储器操作在刷新目标银行。

6. 发明授权

US07668040B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US07668040B2
公开(公告)日：2010-02-23
申请号：US11707252
申请日：2007-02-16
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C7/10
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
摘要翻译：存储器件具有：多个存储体，每个存储体具有存储单元阵列，该存储单元阵列具有分别由行地址选择的多个页面区域，并且每个区域由银行地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。基于列地址访问每个激活的页面区域内的存储单元区域。行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址提供的银行地址和提供的行地址。响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。

7. 发明申请

US20080151678A1 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US20080151678A1
公开(公告)日：2008-06-26
申请号：US11707252
申请日：2007-02-16
申请人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Hitoshi Ikeda , Takahiko Sato , Tatsuya Kanda , Toshiya Uchida , Hiroyuki Kobayashi , Satoru Shirakawa , Tetsuo Miyamoto , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12
CPC分类号： G11C8/12 , G06F12/0207
摘要： The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
摘要翻译：存储器件具有：多个存储体，每个存储体具有分别由行地址选择的多个页面区域的存储单元阵列，并且每个存储单元阵列由存储体地址选择; 行控制器，其响应于第一操作码来控制每个存储体内的页面区域的激活; 和一组数据输入/输出端子。基于列地址访问每个激活的页面区域内的存储单元区域。行控制器响应于与第一命令一起提供的多存储体信息数据和提供的库地址，为多个存储体生成存储体激活信号，并且响应于第一指令生成多个存储体的行地址提供的银行地址和提供的行地址。响应于行激活信号和由行地址计算器生成的行地址，多个存储体激活页面区域。

8. 发明申请

US20080085227A1 MICROREACTOR 失效
公开(公告)号：US20080085227A1
公开(公告)日：2008-04-10
申请号：US11835439
申请日：2007-08-08
申请人： Tetsuo Miyamoto , Hajime Kato , Shigenori Togashi
发明人： Tetsuo Miyamoto , Hajime Kato , Shigenori Togashi
IPC分类号： B01J19/00
CPC分类号： B01F13/0062 , B01F5/0646 , B01F5/0651 , B01F5/0653 , B01F13/0066 , B01F13/1013 , B01F13/1022 , B01J19/0093 , B01J2219/00783 , B01J2219/00889
摘要： The microreactor for mixing and discharging multiple raw material liquids is obtained by laminating: a base plate in which a raw material introducing fluid channel is formed; a raw material introducing plate; and a mixing fluid channel plate which is arranged between the base plate and the raw material introducing plate, and in which a mixing fluid channel is formed. The microreactor includes: a mixing fluid channel in the mixing fluid channel plate which is formed in the mixing fluid channel plate, and in which a flow is contracted in its width direction; and a mixing fluid channel in the base plate which is formed in the base plate, and which has a fluid channel cross-section which becomes larger in its depth direction as it goes downstream. The mixing fluid channel in the base plate communicates with the mixing fluid channel in the mixing fluid channel plate, and is connected to an outlet orifice from which to discharge the mixed liquids.
摘要翻译：用于混合和排出多种原料液体的微反应器通过层压：其中形成有原料引入流体通道的基板; 原材料导入板; 以及设置在基板和原料导入板之间的混合流体通道板，其中形成混合流体通道。微反应器包括：混合流体通道板中的混合流体通道，其形成在混合流体通道板中，并且流体在其宽度方向上收缩; 以及形成在基板中的底板中的混合流体通道，并且具有在其下游沿其深度方向变大的流体通道横截面。基板中的混合流体通道与混合流体通道板中的混合流体通道连通，并连接到排出混合液体的出口孔。

9. 发明授权

US08015389B2 Memory device, memory controller and memory system 有权
标题翻译：内存设备，内存控制器和内存系统
公开(公告)号：US08015389B2
公开(公告)日：2011-09-06
申请号：US12000953
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/06
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
摘要翻译：提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中，在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

10. 发明授权

US07774577B2 Memory device, memory controller and memory system 有权
公开(公告)号：US07774577B2
公开(公告)日：2010-08-10
申请号：US12000952
申请日：2007-12-19
申请人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiko Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G11C8/12 , G06F12/04
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

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