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1. 发明授权

US06928000B2 Semiconductor memory device having a resistance adjustment unit 失效
标题翻译：具有电阻调节单元的半导体存储器件
公开(公告)号：US06928000B2
公开(公告)日：2005-08-09
申请号：US10821840
申请日：2004-04-12
申请人： Yoshikazu Homma , Tetsuji Takeguchi
发明人： Yoshikazu Homma , Tetsuji Takeguchi
IPC分类号： G11C16/06 , G11C7/08 , G11C8/08 , G11C16/08 , G11C16/24 , G11C16/28 , G11C29/02
CPC分类号： G11C29/026 , G11C8/08 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/28 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/1202
摘要： The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.
摘要翻译：本发明提供了一种高速执行高可靠性数据读取操作的半导体存储器件。该半导体存储器件根据从连接到字线的存储单元读出的信号与连接到参考字的参考单元读出的信号的比较结果，读取存储在存储单元中的数据线。该半导体存储器件包括负载能力调整电路，其根据存储器单元与字线的连接的每个位置调整启动参考单元的栅极的定时。

2. 发明授权

US06735120B2 Semiconductor device having a high-speed data read operation 失效
标题翻译：具有高速数据读取操作的半导体器件
公开(公告)号：US06735120B2
公开(公告)日：2004-05-11
申请号：US10345187
申请日：2003-01-16
申请人： Yoshikazu Homma , Tetsuji Takeguchi
发明人： Yoshikazu Homma , Tetsuji Takeguchi
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C8/08 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/28 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/1202
摘要： The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.
摘要翻译：本发明提供了一种高速执行高可靠性数据读取操作的半导体存储器件。该半导体存储器件根据从连接到字线的存储单元读出的信号与连接到参考字的参考单元读出的信号的比较结果，读取存储在存储单元中的数据线。该半导体存储器件包括负载能力调整电路，其根据存储器单元与字线的连接的每个位置调整启动参考单元的栅极的定时。

3. 发明授权

US06532174B2 Semiconductor memory device having high speed data read operation 有权
标题翻译：具有高速数据读取操作的半导体存储器件
公开(公告)号：US06532174B2
公开(公告)日：2003-03-11
申请号：US09739395
申请日：2000-12-19
申请人： Yoshikazu Homma , Tetsuji Takeguchi
发明人： Yoshikazu Homma , Tetsuji Takeguchi
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C8/08 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/28 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/1202
摘要： The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.
摘要翻译：本发明提供了一种高速执行高可靠性数据读取操作的半导体存储器件。该半导体存储器件根据从连接到字线的存储单元读出的信号与连接到参考字的参考单元读出的信号的比较结果，读取存储在存储单元中的数据线。该半导体存储器件包括负载能力调整电路，其根据存储器单元与字线的连接的每个位置调整启动参考单元的栅极的定时。

4. 发明授权

US06215717B1 Semiconductor memory device for reducing a time needed for performing a protecting operation 有权
标题翻译：用于减少执行保护操作所需的时间的半导体存储器件
公开(公告)号：US06215717B1
公开(公告)日：2001-04-10
申请号：US09161262
申请日：1998-09-28
申请人： Tetsuji Takeguchi , Haruo Shoji
发明人： Tetsuji Takeguchi , Haruo Shoji
IPC分类号： G11C800
CPC分类号： G11C7/24 , G11C16/22
摘要： A semiconductor memory device which can reduce a time required for a write-protection setting operation when a plurality of blocks are to be write-protected. A write area of the semiconductor memory device is divided into a predetermined number of blocks each of which is rewritable on an individual block basis. Write-protection information is simultaneously provided to a plurality of blocks that are arbitrarily designated from among the predetermined number of blocks so that the plurality of blocks are simultaneously subjected to the write-protection setting operation.
摘要翻译：一种半导体存储器件，其可以在多个块要被写保护时减少写保护设置操作所需的时间。半导体存储器件的写入区域被划分成预定数量的块，每个块可以以单独块为基础重写。写保护信息同时提供给从预定数量的块中任意指定的多个块，从而使多个块同时进行写保护设置操作。

5. 发明授权

US5631597A Negative voltage circuit for a flash memory 失效
标题翻译：闪存的负电压电路
公开(公告)号：US5631597A
公开(公告)日：1997-05-20
申请号：US445103
申请日：1995-05-19
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21 , G05F1/10
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.
摘要翻译：独立地安装用于实现闪速存储器的负电压电路，并响应于从行解码器发送的信号而选择性地对字线施加。用于指定字线的行解码器不需要安装在负电压电路中。因此，可以减小负电路的规模。

6. 发明授权

US07266015B2 Redundancy substitution method, semiconductor memory device and information processing apparatus 有权
公开(公告)号：US07266015B2
公开(公告)日：2007-09-04
申请号：US11311485
申请日：2005-12-20
申请人： Osamu Iioka , Tetsuji Takeguchi , Hiroshi Mawatari
发明人： Osamu Iioka , Tetsuji Takeguchi , Hiroshi Mawatari
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C7/14 , G11C16/04 , G11C16/3418 , G11C29/50 , G11C29/50004
摘要： A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge loss detecting reference cell has a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, and the charge gain detecting reference cell has a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell. The method subjects a memory cell whose tendency of the charge loss and/or the charge gain is detected to a redundancy substitution.

7. 发明申请

US20070103974A1 Nonvolatile semiconductor memory device performing erase operation that creates narrow threshold distribution 有权
公开(公告)号：US20070103974A1
公开(公告)日：2007-05-10
申请号：US11358206
申请日：2006-02-22
申请人： Tetsuji Takeguchi
发明人： Tetsuji Takeguchi
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to perform a first block erase operation that erases nonvolatile memory cells together in a lump such that threshold voltages of the memory cells are set lower than a first erase verify voltage, to check whether a threshold voltage of each of the nonvolatile memory cells is lower than a first erase-degree-check voltage after the first block erase operation, to perform a first write-back operation in response to a check result indicating that the threshold voltage is lower than the first erase-degree-check voltage, thereby raising the threshold voltage above a voltage higher than the first erase-degree-check voltage, and to perform a second block erase operation that erases the nonvolatile memory cells together in a lump after the first write-back operation such that the threshold voltages of the memory cells are set lower than a second erase verify voltage.

8. 发明授权

US5576637A XOR CMOS logic gate 失效
标题翻译：异或CMOS逻辑门
公开(公告)号：US5576637A
公开(公告)日：1996-11-19
申请号：US441460
申请日：1995-05-15
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input. The gates of the second and fourth nMIS transistors and the second and fourth pMIS transistors are connected to one another and provided with a second input. The sources of the second and third nMIS transistors are connected to each other and provide the exclusive OR of the first and second inputs.
摘要翻译：异或电路包括第一串联电路，其中第一pMIS晶体管的源极连接到正电压电源线。第一pMIS晶体管的漏极经由第二nMIS晶体管连接到第一nMIS晶体管的漏极。第一nMIS晶体管的源极经由第四nMIS晶体管连接到低压电源线。第二串联电路具有通过第二pMIS晶体管连接到高压电源线的第三nMIS晶体管的漏极。第三个nMIS晶体管的源极连接到第三个pMIS晶体管的源极。第三个pMIS晶体管的漏极通过第四个pMIS晶体管连接到低压电源线。第一和第三nMIS晶体管和第一和第三pMIS晶体管的栅极彼此连接并提供有第一输入。第二和第四nMIS晶体管和第二和第四pMIS晶体管的栅极彼此连接并提供有第二输入。第二和第三nMIS晶体管的源极彼此连接并提供第一和第二输入的异或。

9. 发明授权

US07227784B2 Nonvolatile semiconductor memory device performing erase operation that creates narrow threshold distribution 有权
标题翻译：执行产生窄阈值分布的擦除操作的非易失性半导体存储器件
公开(公告)号：US07227784B2
公开(公告)日：2007-06-05
申请号：US11358206
申请日：2006-02-22
申请人： Tetsuji Takeguchi
发明人： Tetsuji Takeguchi
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to perform a first block erase operation that erases nonvolatile memory cells together in a lump such that threshold voltages of the memory cells are set lower than a first erase verify voltage, to check whether a threshold voltage of each of the nonvolatile memory cells is lower than a first erase-degree-check voltage after the first block erase operation, to perform a first write-back operation in response to a check result indicating that the threshold voltage is lower than the first erase-degree-check voltage, thereby raising the threshold voltage above a voltage higher than the first erase-degree-check voltage, and to perform a second block erase operation that erases the nonvolatile memory cells together in a lump after the first write-back operation such that the threshold voltages of the memory cells are set lower than a second erase verify voltage.
摘要翻译：非易失性半导体存储器件包括控制电路，其被配置为执行将非易失性存储单元一齐擦除的第一块擦除操作，使得存储器单元的阈值电压被设置为低于第一擦除验证电压，以检查阈值电压每个非易失性存储单元的电位低于第一块擦除操作之后的第一擦除度检查电压，以响应于指示阈值电压低于第一擦除的检查结果执行第一回写操作从而将阈值电压提高到高于第一擦除度检查电压的电压以上，并且执行在第一回写操作之后一次性地将非易失性存储单元一起擦除的第二块擦除操作使得存储器单元的阈值电压被设置为低于第二擦除验证电压。

10. 发明授权

US5770963A Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有改进的可擦除性及其电路
公开(公告)号：US5770963A
公开(公告)日：1998-06-23
申请号：US436699
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21 , H03K5/08
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.
摘要翻译：闪存通过向控制栅极施加负电压来执行信道擦除或源擦除。该装置包括限制施加到控制栅极的负电压的电压限制装置，使得负电压相对于通道或源的电压将是恒定值。或者，两个电压限制装置限制施加到控制栅极的负电压和施加到源极的电压，使得电压相对于公共参考电压将是恒定值。

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