专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07594208B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07594208B1
公开(公告)日：2009-09-22
申请号：US11610392
申请日：2006-12-13
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

2. 发明授权

US07464362B1 Method and apparatus for performing incremental compilation 有权
标题翻译：用于执行增量编译的方法和装置
公开(公告)号：US07464362B1
公开(公告)日：2008-12-09
申请号：US11384962
申请日：2006-03-20
申请人： Terry Borer , David Karchmer , Jason Govig , Andrew Leaver , Gabriel Quan , Kevin Chan , Vaughn Betz , Stephen D. Brown
发明人： Terry Borer , David Karchmer , Jason Govig , Andrew Leaver , Gabriel Quan , Kevin Chan , Vaughn Betz , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.
摘要翻译：一种用于在目标设备上设计系统的方法包括将用于系统的第一分区的后拟合网表从设置编译与用于系统的第二分区的后合成网表从递增编译合并形成组合网表。组合网表进行配对。

3. 发明授权

US07401314B1 Method and apparatus for performing compound duplication of components on field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列上执行组件复合复制的方法和装置
公开(公告)号：US07401314B1
公开(公告)日：2008-07-15
申请号：US11148588
申请日：2005-06-09
申请人： Karl Schabas , Stephen Brown , Deshanand Singh , Terry Borer , Shawn Malhotra
发明人： Karl Schabas , Stephen Brown , Deshanand Singh , Terry Borer , Shawn Malhotra
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes duplicating a plurality of components in response to slack values associated with connections to the components in placement locations.
摘要翻译：使用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括响应于与放置位置中的组件的连接相关联的松弛值复制多个组件。

4. 发明授权

US08370776B1 Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow 有权
标题翻译：使用增量编译设计流程编制知识产权制度设计核心的方法和装置
公开(公告)号：US08370776B1
公开(公告)日：2013-02-05
申请号：US12157809
申请日：2008-06-13
申请人： Kevin Chan , Terry Borer
发明人： Kevin Chan , Terry Borer
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/66
摘要： A method for designing a system on a target device includes compiling an intellectual property (IP) core to be implemented on the target device such that it satisfies user specified requirements for the system. User logic is compiled after the IP core has been compiled to satisfy user specified requirements for the system.
摘要翻译：在目标设备上设计系统的方法包括编译要在目标设备上实现的知识产权（IP）核，使其满足用户对系统的要求。在编译IP内核以满足用户对系统的要求后，编译用户逻辑。

5. 发明授权

US07594204B1 Method and apparatus for performing layout-driven optimizations on field programmable gate arrays 失效
标题翻译：用于在现场可编程门阵列上执行布局驱动优化的方法和装置
公开(公告)号：US07594204B1
公开(公告)日：2009-09-22
申请号：US10679593
申请日：2003-10-06
申请人： Deshanand Singh , Paul McHardy , Chris Sanford , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Ivan Hamer , Stephen D. Brown
发明人： Deshanand Singh , Paul McHardy , Chris Sanford , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Ivan Hamer , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.
摘要翻译：使用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括识别与系统中的关键信号相关联的一组组件。产生组件组的第一副本和第二副本，其中第一副本由第一状态的第一信号驱动，第二副本由第二状态的第二信号驱动。该系统被配置为响应于关键信号选择第一副本和第二副本之一的输出。

6. 发明授权

US08037435B1 Directed design space exploration 有权
标题翻译：定向设计空间探索
公开(公告)号：US08037435B1
公开(公告)日：2011-10-11
申请号：US12116136
申请日：2008-05-06
申请人： Ian Chesal , Terry Borer
发明人： Ian Chesal , Terry Borer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/08
摘要： The time and computational resources needed to evaluate the potential input parameter settings in a design space is decreased by determining probabilities of improvement for input parameter settings in the design space and eliminating input parameter values that have low probabilities of improvement from the design space prior to compilation. The probability of improvement for input parameter settings is an estimate of the likelihood that the compilation of the user design using the set of input parameter settings will improve the performance of the user design with respect to one or more design goals, such as timing, power, or resource usage. The probability of improvement for input parameter settings can be determined from an analysis of the compilation results of sample designs, from attributes and/or constraints of the user design, and/or from a correlation between the results of optimization algorithms applied to the user design.
摘要翻译：通过确定设计空间中输入参数设置的改进概率，消除编译之前设计空间改进概率低的输入参数值，可以减少设计空间中潜在的输入参数设置所需的时间和计算资源。。输入参数设置的改进概率是对使用该组输入参数设置的用户设计的编译将改善用户设计相对于一个或多个设计目标的性能（例如定时，功率）的可能性的估计，或资源使用。输入参数设置的改进概率可以从样本设计的编译结果，用户设计的属性和/或约束条件的分析和/或从应用于用户设计的优化算法的结果之间的相关性来确定。

7. 发明授权

US07669157B1 Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches 有权
标题翻译：使用自上而下和自下而上设计方法执行增量编译的方法和装置
公开(公告)号：US07669157B1
公开(公告)日：2010-02-23
申请号：US11515561
申请日：2006-09-05
申请人： Terry Borer , Andrew Leaver , David Karchmer , Gabriel Quan , Stephen D. Brown
发明人： Terry Borer , Andrew Leaver , David Karchmer , Gabriel Quan , Stephen D. Brown
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5054 , G01R31/318364 , G06F17/5045 , G06F17/505 , G06F17/5072 , G06F2217/04 , G06F2217/86
摘要： A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.
摘要翻译：一种用于在目标设备上设计系统的方法包括将从自下而上的设计流程生成的系统的第一分区的网表与用于系统的第二分区的网表从上到下的设计流程合并，形成组合网表，并在组合网表上执行拟合。

8. 发明授权

US07370295B1 Directed design space exploration 失效
标题翻译：定向设计空间探索
公开(公告)号：US07370295B1
公开(公告)日：2008-05-06
申请号：US11187076
申请日：2005-07-21
申请人： Ian Chesal , Terry Borer
发明人： Ian Chesal , Terry Borer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/08
摘要： The time and computational resources needed to evaluate the potential input parameter settings in a design space is decreased by determining probabilities of improvement for input parameter settings in the design space and eliminating input parameter values that have low probabilities of improvement from the design space prior to compilation. The probability of improvement for input parameter settings is an estimate of the likelihood that the compilation of the user design using the set of input parameter settings will improve the performance of the user design with respect to one or more design goals, such as timing, power, or resource usage. The probability of improvement for input parameter settings can be determined from an analysis of the compilation results of sample designs, from attributes and/or constraints of the user design, and/or from a correlation between the results of optimization algorithms applied to the user design.
摘要翻译：通过确定设计空间中输入参数设置的改进概率，消除编译之前设计空间改进概率低的输入参数值，可以减少设计空间中潜在的输入参数设置所需的时间和计算资源。。输入参数设置的改进概率是对使用该组输入参数设置的用户设计的编译将改善用户设计相对于一个或多个设计目标的性能（例如定时，功率）的可能性的估计，或资源使用。输入参数设置的改进概率可以从样本设计的编译结果，用户设计的属性和/或约束条件的分析和/或从应用于用户设计的优化算法的结果之间的相关性来确定。

9. 发明授权

US08589838B1 M/A for performing incremental compilation using top-down and bottom-up design approaches 有权
标题翻译： M / A用于使用自上而下和自下而上的设计方法执行增量编译
公开(公告)号：US08589838B1
公开(公告)日：2013-11-19
申请号：US13545320
申请日：2012-07-10
申请人： Terry Borer , Andrew Leaver , David Karchmer , Gabriel Quan , Stephen D. Brown
发明人： Terry Borer , Andrew Leaver , David Karchmer , Gabriel Quan , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G01R31/318364 , G06F17/5045 , G06F17/505 , G06F17/5072 , G06F2217/04 , G06F2217/86
摘要： A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.
摘要翻译：一种用于在目标设备上设计系统的方法包括将从自下而上的设计流程生成的系统的第一分区的网表与用于系统的第二分区的网表从上到下的设计流程合并，形成组合网表，并在组合网表上执行拟合。

10. 发明授权

US07389489B1 Techniques for editing circuit design files to be compatible with a new programmable IC 失效
标题翻译：用于编辑电路设计文件以与新的可编程IC兼容的技术
公开(公告)号：US07389489B1
公开(公告)日：2008-06-17
申请号：US10840206
申请日：2004-05-05
申请人： Ian Chesal , Kevin Chan , Subianto Windoro , Minh Mac , Terry Borer , Stephen Brown , Irene Sujanto , Sheac Yee Lim
发明人： Ian Chesal , Kevin Chan , Subianto Windoro , Minh Mac , Terry Borer , Stephen Brown , Irene Sujanto , Sheac Yee Lim
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Techniques are provided for converting a circuit design file so that it is compatible with a new programmable IC. Black box declarations and instances of black boxes in the circuit design file are located automatically. Then, information about the function and structure of the black boxes is gathered from various user files. This information is used to convert the black box declarations and instances into equivalent declarations and instances that are compatible with the new programmable IC. The design conversion process is performed quickly and automatically with minimal user input. User input is only needed to identify recognized black boxes.
摘要翻译：提供了用于转换电路设计文件以使其与新的可编程IC兼容的技术。电路设计文件中的黑盒子声明和黑盒子的实例都会自动定位。然后，从各种用户文件收集有关黑匣子的功能和结构的信息。该信息用于将黑盒声明和实例转换为与新的可编程IC兼容的等效声明和实例。设计转换过程以最少的用户输入快速自动执行。用户输入只需要识别识别的黑盒子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式