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1. 发明授权

US07181703B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07181703B1
公开(公告)日：2007-02-20
申请号：US10625505
申请日：2003-07-22
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

2. 发明授权

US07594208B1 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage 有权
标题翻译：在计算机辅助设计中自动扫描参数以实现最佳性能和资源使用的技术
公开(公告)号：US07594208B1
公开(公告)日：2009-09-22
申请号：US11610392
申请日：2006-12-13
申请人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
发明人： Terry Borer , Ian Chesal , James Schleicher , David Mendel , Mike Hutton , Boris Ratchev , Yaska Sankar , Babette van Antwerpen , Gregg Baeckler , Richard Yuan , Stephen Brown , Vaughn Betz , Kevin Chan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.
摘要翻译：提供了用于优化可编程集成电路上的电路设计的放置和合成的技术。在对已选择的输入参数编译不同的值后，对电路设计的性能进行分析。然后选择为输出量度产生最佳结果的输入参数值，以将电路设计合成并将其放置在可编程集成电路上。在一个实施例中，对于共享相同输入参数但是不同种子的所有测试编译器，对输出度量的值进行平均。在另一个实施例中，选择由用户确定的具有最佳输出度量的编译。这些技术允许用户自动交换编译时间以获得更优化的电路。

3. 发明授权

US07389489B1 Techniques for editing circuit design files to be compatible with a new programmable IC 失效
标题翻译：用于编辑电路设计文件以与新的可编程IC兼容的技术
公开(公告)号：US07389489B1
公开(公告)日：2008-06-17
申请号：US10840206
申请日：2004-05-05
申请人： Ian Chesal , Kevin Chan , Subianto Windoro , Minh Mac , Terry Borer , Stephen Brown , Irene Sujanto , Sheac Yee Lim
发明人： Ian Chesal , Kevin Chan , Subianto Windoro , Minh Mac , Terry Borer , Stephen Brown , Irene Sujanto , Sheac Yee Lim
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Techniques are provided for converting a circuit design file so that it is compatible with a new programmable IC. Black box declarations and instances of black boxes in the circuit design file are located automatically. Then, information about the function and structure of the black boxes is gathered from various user files. This information is used to convert the black box declarations and instances into equivalent declarations and instances that are compatible with the new programmable IC. The design conversion process is performed quickly and automatically with minimal user input. User input is only needed to identify recognized black boxes.
摘要翻译：提供了用于转换电路设计文件以使其与新的可编程IC兼容的技术。电路设计文件中的黑盒子声明和黑盒子的实例都会自动定位。然后，从各种用户文件收集有关黑匣子的功能和结构的信息。该信息用于将黑盒声明和实例转换为与新的可编程IC兼容的等效声明和实例。设计转换过程以最少的用户输入快速自动执行。用户输入只需要识别识别的黑盒子。

4. 发明授权

US07464362B1 Method and apparatus for performing incremental compilation 有权
标题翻译：用于执行增量编译的方法和装置
公开(公告)号：US07464362B1
公开(公告)日：2008-12-09
申请号：US11384962
申请日：2006-03-20
申请人： Terry Borer , David Karchmer , Jason Govig , Andrew Leaver , Gabriel Quan , Kevin Chan , Vaughn Betz , Stephen D. Brown
发明人： Terry Borer , David Karchmer , Jason Govig , Andrew Leaver , Gabriel Quan , Kevin Chan , Vaughn Betz , Stephen D. Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.
摘要翻译：一种用于在目标设备上设计系统的方法包括将用于系统的第一分区的后拟合网表从设置编译与用于系统的第二分区的后合成网表从递增编译合并形成组合网表。组合网表进行配对。

5. 发明授权

US08370776B1 Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow 有权
标题翻译：使用增量编译设计流程编制知识产权制度设计核心的方法和装置
公开(公告)号：US08370776B1
公开(公告)日：2013-02-05
申请号：US12157809
申请日：2008-06-13
申请人： Kevin Chan , Terry Borer
发明人： Kevin Chan , Terry Borer
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/66
摘要： A method for designing a system on a target device includes compiling an intellectual property (IP) core to be implemented on the target device such that it satisfies user specified requirements for the system. User logic is compiled after the IP core has been compiled to satisfy user specified requirements for the system.
摘要翻译：在目标设备上设计系统的方法包括编译要在目标设备上实现的知识产权（IP）核，使其满足用户对系统的要求。在编译IP内核以满足用户对系统的要求后，编译用户逻辑。

6. 发明授权

US07257800B1 Method and apparatus for performing logic replication in field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列中执行逻辑复制的方法和装置
公开(公告)号：US07257800B1
公开(公告)日：2007-08-14
申请号：US10806617
申请日：2004-06-24
申请人： Deshanand Singh , Gabriel Quan , Terry Borer , Valavan Manohararajah , Paul McHardy , Ivan Hamer , Karl Schabas , Kevin Chan
发明人： Deshanand Singh , Gabriel Quan , Terry Borer , Valavan Manohararajah , Paul McHardy , Ivan Hamer , Karl Schabas , Kevin Chan
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.
摘要翻译：公开了一种使用现场可编程门阵列在目标设备上设计系统的方法。为系统合成了一个设计。设计中的组件映射到目标设备上的资源。确定目标设备上的组件的位置位置。根据从放置位置确定的关键性来识别要复制的组件。

7. 发明授权

US07191426B1 Method and apparatus for performing incremental compilation on field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列上执行增量编译的方法和装置
公开(公告)号：US07191426B1
公开(公告)日：2007-03-13
申请号：US10931953
申请日：2004-09-01
申请人： Deshanand Singh , Stephen Brown , Kevin Chan
发明人： Deshanand Singh , Stephen Brown , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes generating a first design for the system that includes a first netlist describing a first logical design, and placement and routing of the first logical design. A second design for the system is generated that includes a second netlist describing a second logical design. Changes made to the first design in the second design are identified. Placement is performed on the changes made to the first design on the second design.
摘要翻译：利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括为系统生成包括描述第一逻辑设计的第一网表以及第一逻辑设计的布局和路由的系统的第一设计。生成系统的第二设计，其包括描述第二逻辑设计的第二网表。确定了第二个设计中对第一个设计所做的更改。对第二次设计上对第一个设计所做的更改执行放置。

8. 发明申请

US20210137242A1 STICK PRODUCT REFILL SYSTEM 有权
公开(公告)号：US20210137242A1
公开(公告)日：2021-05-13
申请号：US16679892
申请日：2019-11-11
申请人： Kevin Chan
发明人： Kevin Chan
IPC分类号： A45D40/06 , B29C39/38 , B29C39/02 , B29C69/00
摘要： A system for refilling a stick product, such as lipstick or deodorant, in a propel-repel dispenser allows the reuse of the propel-repel mechanism. The stick product refill is shaped and dimensioned to be inserted into the open end of the dispenser and to attach to the receptacle that holds the stick product after the used product has been removed. Attachment of the refill to the stick receptacle is by an attachment means on the outer surface of an anchor cap enclosing the distal end of the refill and/or on the receptacle itself. Once secured to the receptacle, the refill can be advanced and retracted by the propel-repel mechanism so that it protrudes when in use and is withdrawn with the dispenser to protect it when not in use.

9. 发明授权

US08924974B1 System for error checking of process definitions for batch processes 有权
标题翻译：用于批处理流程定义的错误检查系统
公开(公告)号：US08924974B1
公开(公告)日：2014-12-30
申请号：US13156276
申请日：2011-06-08
申请人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
发明人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/4843 , G06F9/4881
摘要： A system for processing a batch job comprises a processor and a memory. The processor is configured to receive a batch job comprising a sequential or parallel flow of operations, wherein each operation has a defined input type and a defined output type. The processor is further configured to verify that the batch job can run successfully, wherein verifying includes checking that a first operation output defined type is compatible with a second operation input defined type when a first operation output is connected to a second operation input, and wherein verifying includes checking that a parameter used by a calculation in an operation is input to the operation. The memory is coupled to the processor and configured to provide the processor with instructions.
摘要翻译：用于处理批处理作业的系统包括处理器和存储器。处理器被配置为接收包括顺序或并行的操作流的批处理作业，其中每个操作具有定义的输入类型和定义的输出类型。处理器还被配置为验证批处理作业可以成功运行，其中，当第一操作输出连接到第二操作输入时，验证包括检查第一操作输出定义类型是否与第二操作输入定义类型兼容，并且其中验证包括检查操作中的计算使用的参数是否被输入到操作中。存储器耦合到处理器并且被配置为向处理器提供指令。

10. 发明授权

US08769537B1 System for partitioning batch processes 有权
标题翻译：用于分批批处理的系统
公开(公告)号：US08769537B1
公开(公告)日：2014-07-01
申请号：US13156278
申请日：2011-06-08
申请人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
发明人： Jonathan Ruggiero , Salvador Maiorano Quiroga , Kevin Chan , Christopher Speer
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/46 , G06F9/5027
摘要： A system for processing a batch job comprises a processor and a memory. The processor is configured to receive a job name for a job submitted to execute, to receive one or more job parameters, and to determine one or more nodes to run the job. The processor is configured to determine one or steps, where for each step: a step is executed on a node using a state of data associated with a start state of the step; and upon completion of executing the step, a result is stored to a durable storage. The durable storage stores the state of data associated with the start state of the step and the completion state of the step and are accessible by other execution processes as associated with either the start state of the step or the completion state of the step. The memory of the system is coupled to the processor and configured to provide processor with instructions.
摘要翻译：用于处理批处理作业的系统包括处理器和存储器。处理器被配置为接收为执行提交的作业的作业名，以接收一个或多个作业参数，并且确定一个或多个节点来运行作业。处理器被配置为确定一个或多个步骤，其中对于每个步骤：使用与步骤的开始状态相关联的数据状态在节点上执行步骤; 并且在执行步骤完成时，将结果存储到耐用存储器中。持久存储器存储与步骤的开始状态和步骤的完成状态相关联的数据的状态，并且可以由步骤的开始状态或步骤的完成状态相关联的其他执行过程访问。系统的存储器耦合到处理器并且被配置为向处理器提供指令。

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