专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120239996A1 MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING MEMORY CONTROLLER 审中-公开
标题翻译：存储器控制器，信息处理装置和控制存储器控制器的方法
公开(公告)号：US20120239996A1
公开(公告)日：2012-09-20
申请号：US13402284
申请日：2012-02-22
申请人： Masanori HIGETA , Hiroshi Nakayama , Hidekazu Osano , Hideyuki Sakamaki , Kazuya Takaku
发明人： Masanori HIGETA , Hiroshi Nakayama , Hidekazu Osano , Hideyuki Sakamaki , Kazuya Takaku
IPC分类号： G06F11/07
CPC分类号： G06F11/1048
摘要： A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data.
摘要翻译：连接到具有ECC（错误检查和校正）功能并且控制对存储器模块的访问的存储器模块的存储器控制器，存储器控制器具有错误检测单元，其被配置为检测错误位和错误的位置通过从存储器模块读取与从存储器模块读取的多个读取数据相对应的ECC的代码的信息，配置为临时存储多个读取数据的缓冲器，以及确定单元，存储在缓冲器中的多个读取数据包括由错误检测单元检测到可校正错误的数据的数量，并且检测到的数据的错误检测位置彼此相同，可纠正错误被包括在一组多个读取数据。

2. 发明授权

US08321736B2 Transmission system, transmission method and communication device 失效
标题翻译：传输系统，传输方式和通信设备
公开(公告)号：US08321736B2
公开(公告)日：2012-11-27
申请号：US12410074
申请日：2009-03-24
申请人： Masanori Higeta , Kenji Suzuki
发明人： Masanori Higeta , Kenji Suzuki
IPC分类号： G06F11/00
CPC分类号： H04L1/1829 , G06F11/1443
摘要： A transmission method for transmitting information between a transmission device and a reception device, the method includes determining whether or not an error is detected in information from the transmission device, requesting the transmission device to re-transmit the error-detected information when an error is detected, re-transmitting information corresponding to a re-transmission request as re-transmission information from the transmission device when the re-transmission request is detected, registering the re-transmission information as a test pattern, transmitting the registered test pattern to the reception device, registering the re-transmission data received from the transmission device as a collation pattern, reading out the collation pattern corresponding to the received test pattern, and collating the test pattern and the collation pattern when a test pattern is received from the transmission device, and adjusting and setting a parameter of the reception device on the basis of a pattern collation result.
摘要翻译：一种用于在发送装置和接收装置之间发送信息的发送方法，所述方法包括：确定在来自发送装置的信息中是否检测到错误，请求发送装置在发生错误的情况下重新发送错误检测信息检测到，当检测到重发请求时，将来自发送设备的重传信息作为重发信息重新发送，将该再发送信息登记为测试模式，将登记的测试模式发送到接收将从发送装置接收到的再发送数据登录为核对模式，读取与接收到的测试模式对应的核对模式，并且当从发送装置接收到测试模式时对照测试模式和对照模式，并且在底座上调整和设置接收设备的参数是一种模式整理结果。

3. 发明申请

US20110228827A1 Receiving apparatus, transmission apparatus, and transmission methods 失效
标题翻译：接收装置，传输装置和传输方法
公开(公告)号：US20110228827A1
公开(公告)日：2011-09-22
申请号：US13067368
申请日：2011-05-26
申请人： Masanori Higeta
发明人： Masanori Higeta
IPC分类号： H04B1/38 , H04B1/06
CPC分类号： H04L7/033 , H03K5/1534 , H03K5/26 , H04L7/0008 , H04L7/10
摘要： A receiving apparatus includes a first receiving circuit that receives an input signal based on a clock signal, and outputs a first output signal, a second receiving circuit that receives the input signal based on the clock signal, and outputs a second output signal, and a comparison circuit that compares value of the first output signal outputted by the first receiving circuit and value of the second output signal outputted by the second receiving circuit.
摘要翻译：接收装置包括：第一接收电路，其基于时钟信号接收输入信号，并输出第一输出信号;基于时钟信号接收输入信号的第二接收电路，并输出第二输出信号;以及比较由第一接收电路输出的第一输出信号和由第二接收电路输出的第二输出信号的值的比较电路。

4. 发明申请

US20100106901A1 MEMORY REFRESHING APPARATUS AND METHOD FOR MEMORY REFRESH 失效
标题翻译：内存刷新装置和存储器刷新方法
公开(公告)号：US20100106901A1
公开(公告)日：2010-04-29
申请号：US12683059
申请日：2010-01-06
申请人： Masanori HIGETA , Kenji Suzuki , Takatsugu Sasaki
发明人： Masanori HIGETA , Kenji Suzuki , Takatsugu Sasaki
IPC分类号： G06F12/06
CPC分类号： G11C11/406 , G06F11/106 , G11C11/401 , G11C29/028 , G11C29/50016 , G11C29/52 , G11C2029/0409 , G11C2211/4061
摘要： The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.
摘要翻译：刷新周期的优化与存储器中的错误发生状态相一致地执行，存在正常巡视控制部分，其控制巡视存储器的正常巡视操作; 如果在正常巡视操作期间检测到存储器中的第一错误，则发生第一错误并且包括在存储器中的错误发生区域的附加巡检控制部分，其控制附加巡视操作，测量部分，测量在所述附加巡视操作期间在所述错误发生区域中检测到第二误差的误差频率，所述误差频率表示所述错误发生区域中的误差信息; 以及刷新周期调整部，其根据由测量部测量的误差频率来调整刷新周期。

5. 发明授权

US08549366B2 Memory refreshing circuit and method for memory refresh 失效
标题翻译：内存刷新电路和内存刷新方法
公开(公告)号：US08549366B2
公开(公告)日：2013-10-01
申请号：US12683059
申请日：2010-01-06
申请人： Masanori Higeta , Kenji Suzuki , Takatsugu Sasaki
发明人： Masanori Higeta , Kenji Suzuki , Takatsugu Sasaki
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11C11/406 , G06F11/106 , G11C11/401 , G11C29/028 , G11C29/50016 , G11C29/52 , G11C2029/0409 , G11C2211/4061
摘要： The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section (15) measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.
摘要翻译：刷新周期的优化与存储器中的错误发生状态相一致地执行，存在正常巡视控制部分，其控制巡视存储器的正常巡视操作; 如果在正常巡视操作期间检测到存储器中的第一错误，则发生第一错误并且包括在存储器中的错误发生区域的附加巡检控制部分，其控制附加巡视操作，测量部分，测量在所述附加巡视操作期间在所述错误发生区域中检测到第二误差的误差频率，所述误差频率表示所述错误发生区域中的误差信息; 以及刷新周期调整部，其根据由测量部测量的误差频率来调整刷新周期。

6. 发明授权

US08732532B2 Memory controller and information processing system for failure inspection 有权
标题翻译：内存控制器和信息处理系统进行故障检测
公开(公告)号：US08732532B2
公开(公告)日：2014-05-20
申请号：US13226672
申请日：2011-09-07
申请人： Masanori Higeta
发明人： Masanori Higeta
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/073 , G06F11/076 , G06F11/1048 , G06F2213/0038
摘要： An information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, cause the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.
摘要翻译：一种信息处理系统，包括具有多个单元存储区域的存储器模块，经由存储器接口连接到存储器模块的存储器控制器，被配置为控制对存储器模块的访问，存储器控制器中的错误检测器被配置对从存储器模块读取的数据执行错误检测，故障检查控制器被配置为将存储器控制器的模式从正常模式切换到故障检查模式，从要被检查的数据写入的地址读取数据对于所述多个单元存储区域中的每一个，使得所述错误检测器检测所述读取数据中的错误并执行故障检查，以及确定单元，被配置为基于所述多个单元存储区域的状态来确定存储器故障或传输路径故障从单元存储器区域检测到错误。

7. 发明授权

US08391436B2 Receiving apparatus, transmission apparatus, and transmission method 失效
标题翻译：接收装置，发送装置和发送方法
公开(公告)号：US08391436B2
公开(公告)日：2013-03-05
申请号：US13067368
申请日：2011-05-26
申请人： Masanori Higeta
发明人： Masanori Higeta
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033 , H03K5/1534 , H03K5/26 , H04L7/0008 , H04L7/10
摘要： A receiving apparatus includes a first receiving circuit that receives an input signal based on a clock signal, and outputs a first output signal, a second receiving circuit that receives the input signal based on the clock signal, and outputs a second output signal, and a comparison circuit that compares value of the first output signal outputted by the first receiving circuit and value of the second output signal outputted by the second receiving circuit.
摘要翻译：接收装置包括：第一接收电路，其基于时钟信号接收输入信号，并输出第一输出信号;基于时钟信号接收输入信号的第二接收电路，并输出第二输出信号;以及比较由第一接收电路输出的第一输出信号和由第二接收电路输出的第二输出信号的值的比较电路。

8. 发明申请

US20120131382A1 MEMORY CONTROLLER AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：内存控制器和信息处理系统
公开(公告)号：US20120131382A1
公开(公告)日：2012-05-24
申请号：US13226672
申请日：2011-09-07
申请人： Masanori HIGETA
发明人： Masanori HIGETA
IPC分类号： G06F11/28 , G06F11/20 , G06F11/07
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/073 , G06F11/076 , G06F11/1048 , G06F2213/0038
摘要： A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.
摘要翻译：信息处理系统包括具有多个单元存储区域的存储器模块，经由存储器接口连接到存储器模块的存储器控制器，被配置为控制对存储器模块的访问，存储器控制器中的错误检测器被配置对从存储器模块读取的数据执行错误检测，故障检查控制器被配置为将存储器控制器的模式从正常模式切换到故障检查模式，从要被检查的数据写入的地址读取数据对于所述多个单元存储区域中的每一个，使得所述错误检测器检测所述读取数据中的错误并执行故障检查，以及确定单元，被配置为基于所述多个单元存储区域的状态来确定存储器故障或传输路径故障从单元存储器区域检测到错误。

9. 发明申请

US20090249152A1 TRANSMISSION SYSTEM, TRANSMISSION METHOD AND COMMUNICATION DEVICE 失效
标题翻译：传输系统，传输方法和通信设备
公开(公告)号：US20090249152A1
公开(公告)日：2009-10-01
申请号：US12410074
申请日：2009-03-24
申请人： Masanori HIGETA , Kenji SUZUKI
发明人： Masanori HIGETA , Kenji SUZUKI
IPC分类号： H04L1/08 , G06F11/14
CPC分类号： H04L1/1829 , G06F11/1443
摘要： A transmission method for transmitting information between a transmission device and a reception device, the method includes determining whether or not an error is detected in information from the transmission device, requesting the transmission device to re-transmit the error-detected information when an error is detected, re-transmitting information corresponding to a re-transmission request as re-transmission information from the transmission device when the re-transmission request is detected, registering the re-transmission information as a test pattern, transmitting the registered test pattern to the reception device, registering the re-transmission data received from the transmission device as a collation pattern, reading out the collation pattern corresponding to the received test pattern, and collating the test pattern and the collation pattern when a test pattern is received from the transmission device, and adjusting and setting a parameter of the reception device on the basis of a pattern collation result.
摘要翻译：一种用于在发送装置和接收装置之间发送信息的发送方法，所述方法包括：确定在来自发送装置的信息中是否检测到错误，请求发送装置在发生错误的情况下重新发送错误检测信息检测到，当检测到重发请求时，将来自发送设备的重传信息作为重发信息重新发送，将该再发送信息登记为测试模式，将登记的测试模式发送到接收将从发送装置接收到的再发送数据登录为核对模式，读取与接收到的测试模式对应的核对模式，并且当从发送装置接收到测试模式时对照测试模式和对照模式，并且在底座上调整和设置接收设备的参数是一种模式整理结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式