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1. 发明授权

US08009504B2 Semiconductor memory input/output device 有权
标题翻译：半导体存储器输入/输出装置
公开(公告)号：US08009504B2
公开(公告)日：2011-08-30
申请号：US12339389
申请日：2008-12-19
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C7/22
摘要： A semiconductor memory input/output device includes selection pads used to input and output signals for multiple operation modes and having multiple functions, a control signal generator for outputting setting signals and a mask control signal, a lower input/output unit including a lower output buffer for outputting a read data strobe signal to a selection pad and a lower input buffer for receiving a lower data mask signal from the selection pad, and selecting one operation of the lower output buffer and the lower input buffer, and an upper input/output unit including an upper output buffer for outputting an inverted read data strobe signal to the second selection pad and an upper input buffer for receiving an upper data mask signal from the second selection pad, and selecting one operation of the upper output buffer and the upper input buffer.
摘要翻译：半导体存储器输入/输出装置包括用于输入和输出用于多个操作模式的信号并具有多个功能的选择焊盘，用于输出设置信号的控制信号发生器和掩模控制信号，包括下部输出缓冲器用于将选择焊盘的读取数据选通信号输出到选择焊盘的下部数据屏蔽信号，以及选择下部输出缓冲器和下部输入缓冲器的一个动作，以及上部输入输出部包括用于向第二选择焊盘输出反转的读数据选通信号的上输出缓冲器和用于从第二选择焊盘接收上数据掩码信号的上输入缓冲器，以及选择上输出缓冲器和上输入缓冲器的一个操作。

2. 发明授权

US07759981B2 Amplifying circuit of semiconductor integrated circuit 失效
标题翻译：半导体集成电路放大电路
公开(公告)号：US07759981B2
公开(公告)日：2010-07-20
申请号：US11819610
申请日：2007-06-28
申请人： Sung-Joo Ha
发明人： Sung-Joo Ha
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H03F3/45179 , H03F2200/135 , H03F2203/45366 , H03F2203/45396 , H03F2203/45562 , H03K3/356139
摘要： An amplifying circuit of a semiconductor integrated circuit includes a data amplifier that outputs an up-signal and a down-signal amplified according to a comparison result between an up-data signal and a down-data signal in response to a control signal. The data amplifier repeats an operation of amplifying the up-signal and the down-signal according to the comparison result between the up-signal and the down-signal to be fed back to the data amplifier.
摘要翻译：半导体集成电路的放大电路包括数据放大器，其响应于控制信号，输出根据上位数据信号和下行数据信号之间的比较结果放大的上变频信号和下变频信号。数据放大器根据要反馈到数据放大器的上升信号和下降信号之间的比较结果重复放大上行信号和下降信号的操作。

3. 发明授权

US07573757B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07573757B2
公开(公告)日：2009-08-11
申请号：US12073294
申请日：2008-03-04
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C11/063
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： Disclosed herein is a semiconductor memory device for reducing a current consumption used for operating a write command or a read command. The semiconductor memory device includes a global data latch unit for latching a global data loaded on a global data line in response to a first write enable signal to thereby generate a global latch data; a local data write driving unit for receiving the global latch data to output a local data to a local data line in response to a second write enable signal; and a write driver control unit for generating the first write enable signal and the second write enable signal to inactivate the first write enable signal when a write operation is not performed.
摘要翻译：这里公开了一种用于减少用于操作写入命令或读取命令的电流消耗的半导体存储器件。半导体存储器件包括全局数据锁存单元，用于响应于第一写使能信号来锁存加载在全局数据线上的全局数据，从而生成全局锁存数据; 本地数据写驱动单元，用于接收全局锁存数据，以响应于第二写使能信号将本地数据输出到本地数据线; 以及写入驱动器控制单元，用于在不执行写入操作时产生第一写入使能信号和第二写入使能信号以使第一写入使能信号失活。

4. 发明授权

US07573755B2 Data amplifying circuit for semiconductor integrated circuit 失效
标题翻译：半导体集成电路数据放大电路
公开(公告)号：US07573755B2
公开(公告)日：2009-08-11
申请号：US11822813
申请日：2007-07-10
申请人： Sung-Joo Ha
发明人： Sung-Joo Ha
IPC分类号： G11C7/08
CPC分类号： H03K3/356113 , G11C29/02 , G11C29/028
摘要： A data amplifying circuit for a semiconductor integrated circuit including a controller configured to generate a control signal for adjusting an amplification step in response to a test signal, and a data amplifier configured to amplify an input signal one time or two or more times in response to the control signal and to output an output signal.
摘要翻译：一种用于半导体集成电路的数据放大电路，包括：控制器，被配置为响应于测试信号产生用于调整放大步长的控制信号;以及数据放大器，被配置为响应于一个或多个时间来放大输入信号一次或两次或更多次控制信号并输出输出信号。

5. 发明授权

US07489585B2 Global signal driver for individually adjusting driving strength of each memory bank 失效
标题翻译：用于单独调整每个存储体的驱动强度的全局信号驱动器
公开(公告)号：US07489585B2
公开(公告)日：2009-02-10
申请号：US11478117
申请日：2006-06-30
申请人： Sung-Joo Ha , Yong-Mi Kim
发明人： Sung-Joo Ha , Yong-Mi Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1048 , G11C11/4096 , G11C2207/2254
摘要： A global signal driving device includes a driving control unit for generating a plurality of driving control signals differently configured according to transmission distances of a global signal to a plurality of banks by decoding a bank address; and a driving unit for adjusting a driving strength for driving the global signal based on the plurality of driving control signals in order to drive the global signal to the plurality of banks.
摘要翻译：全局信号驱动装置包括：驱动控制单元，用于通过解码存储体地址来产生根据全局信号到多个存储体的传输距离不同地配置的多个驱动控制信号; 以及驱动单元，用于基于所述多个驱动控制信号来调整用于驱动全局信号的驱动强度，以便将全局信号驱动到多个存储体。

6. 发明授权

US07359256B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07359256B2
公开(公告)日：2008-04-15
申请号：US11312610
申请日：2005-12-21
申请人： Sung-Joo Ha , Ho-Youb Cho
发明人： Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1087 , G11C7/1093 , G11C7/1096
摘要： Disclosed herein is a semiconductor memory device for reducing a current consumption used for operating a write command or a read command. The semiconductor memory device includes a global data latch unit for latching a global data loaded on a global data line in response to a first write enable signal to thereby generate a global latch data; a local data write driving unit for receiving the global latch data to output a local data to a local data line in response to a second write enable signal; and a write driver control unit for generating the first write enable signal and the second write enable signal to inactivate the first write enable signal when a write operation is not performed.
摘要翻译：这里公开了一种用于减少用于操作写入命令或读取命令的电流消耗的半导体存储器件。半导体存储器件包括全局数据锁存单元，用于响应于第一写使能信号来锁存加载在全局数据线上的全局数据，从而生成全局锁存数据; 本地数据写驱动单元，用于接收全局锁存数据，以响应于第二写使能信号将本地数据输出到本地数据线; 以及写入驱动器控制单元，用于在不执行写入操作时产生第一写入使能信号和第二写入使能信号以使第一写入使能信号失活。

7. 发明授权

US07161860B2 Local input/output line precharge circuit of semiconductor memory device 失效
标题翻译：半导体存储器件本地输入/输出线预充电电路
公开(公告)号：US07161860B2
公开(公告)日：2007-01-09
申请号：US11115373
申请日：2005-04-27
申请人： Sung Joo Ha , Ho Youb Cho
发明人： Sung Joo Ha , Ho Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit, an equalization unit and a data output unit. The precharge control unit outputs a precharge control signal to precharge a pair of local input/output lines in response to a continuous write signal activated when a write operation continues. The equalization unit precharges and equalizing the pair of local input/output lines in response to the precharge control signal. The data output unit outputs data signals of a pair of global input/output lines to the pair of local input/output lines in response to output signal from the equalization unit. In the circuit, a local input/output line precharge operation is not performed at a continuous write mode, thereby reducing current consumption.
摘要翻译：半导体存储器件的本地输入/输出线预充电电路包括预充电控制单元，均衡单元和数据输出单元。预充电控制单元输出预充电控制信号，以便在写入操作继续时响应于激活的连续写入信号对一对本地输入/输出线进行预充电。均衡单元响应于预充电控制信号对一对本地输入/输出线进行预充电和均衡。数据输出单元响应于来自均衡单元的输出信号，将一对全局输入/输出线的数据信号输出到一对本地输入/输出线。在该电路中，在连续写入模式下不执行局部输入/输出线预充电操作，从而减少电流消耗。

8. 发明申请

US20050162945A1 Semiconductor memory device having repair circuit 失效
标题翻译：具有修复电路的半导体存储器件
公开(公告)号：US20050162945A1
公开(公告)日：2005-07-28
申请号：US11015419
申请日：2004-12-20
申请人： Sang-Hee Kang , Sung-Joo Ha , Ho-Youb Cho
发明人： Sang-Hee Kang , Sung-Joo Ha , Ho-Youb Cho
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/808
摘要： A semiconductor memory device, including: a plurality of banks each of which includes a plurality of memory cells, a plurality of redundancy memory cells for replacing a defective memory cell and a repair circuit, having a plurality of fuse sets, for substituting an address to thereby access the redundancy memory cell instead of the defective memory cell; and a common repair circuit, having a plurality of fuse sets, for substituting the address in order to replace the defective memory cell with the redundancy memory cell included in any of the plurality of banks.
摘要翻译：一种半导体存储器件，包括：多个存储体，每个存储体包括多个存储单元，用于替换有缺陷存储单元的多个冗余存储单元和具有多个熔丝组的修复电路，用于将地址替换为从而访问冗余存储单元而不是有缺陷的存储单元; 以及具有多个熔丝组的通用修复电路，用于代替所述地址以便用所述多个存储体中的任一个中包含的所述冗余存储单元替换所述有缺陷的存储单元。

9. 发明授权

US08351274B2 Semiconductor memory device and method of precharging the same with a first and second precharge voltage simultaneously applied to a bit line 失效
标题翻译：半导体存储器件及其对第一和第二预充电电压进行预充电同时施加到位线的方法
公开(公告)号：US08351274B2
公开(公告)日：2013-01-08
申请号：US12981927
申请日：2010-12-30
申请人： Sung Joo Ha , Young Soo Park
发明人： Sung Joo Ha , Young Soo Park
IPC分类号： G11C16/24
CPC分类号： G11C16/06 , G11C16/26 , G11C16/32
摘要： A semiconductor memory device includes a memory string coupled between a common source line and a bit line, a page buffer configured to supply a first precharge voltage to the bit line and to latch data corresponding to a threshold voltage level of a memory cell of the memory string, wherein the data is detected according to a shift in a voltage of the bit line, in a precharge operation, a precharge circuit configured to supply a second precharge voltage to the common source line in the precharge operation, and a voltage supply circuit configured to generate operating voltages for turning on the memory string in the precharge operation. While the first precharge voltage is supplied from the page buffer to the bit line, the second precharge voltage is supplied to the bit line through the memory string.
摘要翻译：半导体存储器件包括耦合在公共源极线和位线之间的存储器串，被配置为向位线提供第一预充电电压并锁存对应于存储器的存储器单元的阈值电压电平的数据的页缓冲器串，其中在预充电操作中根据位线的电压的偏移检测数据;预充电电路，被配置为在预充电操作中向公共源极线提供第二预充电电压;以及电压供给电路，以在预充电操作中产生用于接通存储器串的工作电压。当第一预充电电压从页缓冲器提供到位线时，第二预充电电压通过存储器串提供给位线。

10. 发明申请

US20110110167A1 INTEGRATED CIRCUIT 有权
标题翻译：集成电路
公开(公告)号：US20110110167A1
公开(公告)日：2011-05-12
申请号：US13009131
申请日：2011-01-19
申请人： Sung-Joo HA
发明人： Sung-Joo HA
IPC分类号： G11C7/10 , G11C29/00
CPC分类号： G11C29/48 , G11C29/1201
摘要： An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a test operation is activated.
摘要翻译：集成电路包括用于在读/写操作被激活时发送读取数据和在外围区域和核心区域之间写入数据的全局I / O线（GIO），以及用于通过全局来发送/接收测试数据的测试电路 I / O线测试集成电路，当测试操作激活时。

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