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1. 发明授权

US08756558B2 FRAM compiler and layout 有权
标题翻译： FRAM编译器和布局
公开(公告)号：US08756558B2
公开(公告)日：2014-06-17
申请号：US13435718
申请日：2012-03-30
申请人： David J. Toops , Michael P. Clinton
发明人： David J. Toops , Michael P. Clinton
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.
摘要翻译：提供一种用于生成体现在非暂时性存储介质上并由处理器执行的铁电随机存取存储器（FRAM）的布局的计算机程序。接收到FRAM规范，并从非暂时性存储介质中检索FRAM平面图和设计规则。然后组装基于FRAM规范和设计规则的FRAM布局。

2. 发明申请

US20130258751A1 FRAM COMPILER AND LAYOUT 有权
标题翻译：框架编译器和布局
公开(公告)号：US20130258751A1
公开(公告)日：2013-10-03
申请号：US13435718
申请日：2012-03-30
申请人： David J. Toops , Michael P. Clinton
发明人： David J. Toops , Michael P. Clinton
IPC分类号： G11C11/22 , G06F17/50
CPC分类号： G06F17/5068
摘要： A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.
摘要翻译：提供一种用于生成体现在非暂时性存储介质上并由处理器执行的铁电随机存取存储器（FRAM）的布局的计算机程序。接收到FRAM规范，并从非暂时性存储介质中检索FRAM平面图和设计规则。然后组装基于FRAM规范和设计规则的FRAM布局。

3. 发明申请

US20110231736A1 Low-Power Redundancy for Non-Volatile Memory 有权
标题翻译：非易失性存储器的低功耗冗余
公开(公告)号：US20110231736A1
公开(公告)日：2011-09-22
申请号：US12958724
申请日：2010-12-02
申请人： David J. Toops , Sudhir K. Madan , Suresh Balasubramanian
发明人： David J. Toops , Sudhir K. Madan , Suresh Balasubramanian
IPC分类号： G11C7/22 , H03M13/05 , G06F11/10
CPC分类号： G11C29/84 , G06F11/1016 , G11C7/02 , G11C11/22 , G11C29/789 , G11C29/83
摘要： A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.
摘要翻译：用于与诸如铁电RAM（FRAM）的非易失性存储器阵列组合使用的静态RAM冗余存储器，其中减少了SRAM冗余存储器的功耗。冗余存储器的每个字包括数据位单元，用于存储要由冗余元件代替的FRAM阵列中的存储器单元的地址，并且还使能指示是否为这些地址启用冗余的位。给定字中的使能位的逻辑组合确定该字中的数据位单元是否通电。结果，冗余存储器的功耗被降低到对FRAM阵列的段的冗余不起作用的程度。

4. 发明授权

US06731564B1 Method and system for power conservation in memory devices 有权
标题翻译：存储器件节电的方法和系统
公开(公告)号：US06731564B1
公开(公告)日：2004-05-04
申请号：US10391006
申请日：2003-03-18
申请人： Tam M. Tran , George B. Jamison , Bryan D. Sheffield , David J. Toops , Vikas K. Agrawal
发明人： Tam M. Tran , George B. Jamison , Bryan D. Sheffield , David J. Toops , Vikas K. Agrawal
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C2207/002 , G11C2207/005 , G11C2207/2227
摘要： According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.
摘要翻译：根据本发明的一个实施例，提供了可操作以呈现待机模式的存储器电路。存储电路包括一个包括一个门和一个体的晶体管。体积处于保持电压水平。存储器电路还包括由晶体管彼此耦合的第一节点和第二节点。响应于待机模式的启动，第一节点可操作以承担比第二节点更高的电压电平。存储器电路还包括耦合到晶体管的栅极的第三节点。第三节点可操作以响应于待机模式的启动而呈现大致等于保持电压的电压。晶体管可操作以响应于第三节点处的电压升高到大约等于保持电压的电压而减小第一节点和第二节点之间的任何直流电流。

5. 发明授权

US07145822B2 Method and apparatus for optimal write restore for memory 有权
标题翻译：用于存储器最佳写入还原的方法和装置
公开(公告)号：US07145822B2
公开(公告)日：2006-12-05
申请号：US11071012
申请日：2005-03-03
申请人： David J. Toops
发明人： David J. Toops
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit line and a write precharge circuit. The write precharge circuit is operable to provide at least a portion of a charge on the at least one bit line. The column select signal line is operable to provide a column select signal selecting the column for a write operation. The write precharge circuit is gated with the column select signal line such that the column select signal is communicated to the write precharge circuit upon selection of the column for the write operation. The write precharge circuit is operable to at least partially restore the charge on the at least one bit line upon receipt of the column select signal after the write operation.
摘要翻译：根据本发明的一个实施例，存储器子系统包括列和列选择信号线。该列包括至少一个位线和写入预充电电路。写入预充电电路可操作以在至少一个位线上提供电荷的至少一部分。列选择信号线可操作以提供选择用于写操作的列的列选择信号。写入预充电电路与列选择信号线选通，以便在选择用于写入操作的列时将列选择信号传送到写预充电电路。写入预充电电路可操作以在写入操作之后接收到列选择信号时至少部分恢复至少一个位线上的电荷。

6. 发明授权

US5508964A Write recovery time minimization for Bi-CMOS SRAM 失效
标题翻译：为Bi-CMOS SRAM写入恢复时间最小化
公开(公告)号：US5508964A
公开(公告)日：1996-04-16
申请号：US1996
申请日：1993-01-08
申请人： David J. Toops
发明人： David J. Toops
IPC分类号： G11C11/413 , G11C11/419 , G11C7/00
CPC分类号： G11C11/413 , G11C11/419
摘要： A circuit and method for minimizing write recovery time in a Bi-CMOS SRAM by equalizing the bit-line voltages during a read access. A P-channel device whose drain, source and gate are connected to bit, bit-bar, and the write control signal, respectively, indirectly equalizes the bit-lines by equalizing the base voltages of the NPN bit-line load devices only when the column is selected for read access. This technique takes advantage of the current gain of the NPN transistor from the base to the emitter to provide fast bit-line equalization immediately following writes, thus minimizing the write recovery time.
摘要翻译：一种通过在读取访问期间均衡位线电压来最小化Bi-CMOS SRAM中的写恢复时间的电路和方法。其漏极，源极和栅极分别连接到位，位线和写入控制信号的P沟道器件通过均衡NPN位线负载器件的基极电压来间接地均衡位线，只有当列被选择用于读访问。这种技术利用了从基极到发射极的NPN晶体管的电流增益，在写入之后立即提供快速的位线均衡，从而最小化写恢复时间。

7. 发明授权

US08423837B2 High reliability and low power redundancy for memory 有权
标题翻译：高可靠性和低功耗的存储器冗余
公开(公告)号：US08423837B2
公开(公告)日：2013-04-16
申请号：US12705595
申请日：2010-02-13
申请人： Sudhir K. Madan , David J. Toops , Robert J. Landers
发明人： Sudhir K. Madan , David J. Toops , Robert J. Landers
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11C29/76 , G06F11/1048 , G11C29/789 , G11C2029/0411
摘要： An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.
摘要翻译：包含存储器阵列的集成电路，冗余电路和耦合到所述冗余电路的冗余纠错电路。一种用于构造对应于每个存储器段的冗余字的方法和用于在存储器访问请求期间错误地检查冗余字的方法。

8. 发明授权

US08381075B2 Low-power redundancy for non-volatile memory 有权
标题翻译：用于非易失性存储器的低功耗冗余
公开(公告)号：US08381075B2
公开(公告)日：2013-02-19
申请号：US12958724
申请日：2010-12-02
申请人： David J. Toops , Sudhir K. Madan , Suresh Balasubramanian
发明人： David J. Toops , Sudhir K. Madan , Suresh Balasubramanian
IPC分类号： G11C29/00
CPC分类号： G11C29/84 , G06F11/1016 , G11C7/02 , G11C11/22 , G11C29/789 , G11C29/83
摘要： A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.
摘要翻译：用于与诸如铁电RAM（FRAM）的非易失性存储器阵列组合使用的静态RAM冗余存储器，其中减少了SRAM冗余存储器的功耗。冗余存储器的每个字包括数据位单元，用于存储要由冗余元件代替的FRAM阵列中的存储器单元的地址，并且还使能指示是否为这些地址启用冗余的位。给定字中的使能位的逻辑组合确定该字中的数据位单元是否通电。结果，冗余存储器的功耗被降低到对FRAM阵列的段的冗余不起作用的程度。

9. 发明申请

US20100211853A1 High Reliability and Low Power Redundancy for Memory 有权
标题翻译：高可靠性和低功耗的内存冗余
公开(公告)号：US20100211853A1
公开(公告)日：2010-08-19
申请号：US12705595
申请日：2010-02-13
申请人： Sudhir K. Madan , David J. Toops , Robert J. Landers
发明人： Sudhir K. Madan , David J. Toops , Robert J. Landers
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C29/76 , G06F11/1048 , G11C29/789 , G11C2029/0411
摘要： An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request.
摘要翻译：包含存储器阵列的集成电路，冗余电路和耦合到所述冗余电路的冗余纠错电路。一种用于构造对应于每个存储器段的冗余字的方法和用于在存储器访问请求期间错误地检查冗余字的方法。

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