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1. 发明授权

US5470787A Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same 失效
标题翻译：具有形成扩展共晶区域的固有电位的半导体器件焊料凸块及其制造和使用方法
公开(公告)号：US5470787A
公开(公告)日：1995-11-28
申请号：US236320
申请日：1994-05-02
申请人： Stuart E. Greer
发明人： Stuart E. Greer
IPC分类号： H01L21/60 , H01L23/485 , H01L21/44
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： A semiconductor device (32) has an as-deposited solder bump (34) having the intrinsic potential for forming an extended eutectic region for simplified DCA applications. The as-deposited solder bump (34) has first tin layer (40) overlying the UBM of the bonding pad (14) on the device. The first tin layer reacts with a metal layer (36) in the UBM to form an intermetallic for adhering the solder bump to the bonding pad. A thick lead layer (42) overlies the first tin layer to provide the substantial component of the solder bump. A second tin layer (44) overlies the lead layer to provide localized eutectic formation at the top surface of the bump during reflow. A device having at least this solder bump structure can be directly attached to either ceramic or PC board substrates. Additional layers of tin and /or lead may be supplemented to the basic bump structure to optimize the eutectic formation rate.
摘要翻译：半导体器件（32）具有用于形成用于简化DCA应用的扩展共晶区域的固有电位的沉积焊料凸块（34）。沉积的焊料凸块（34）具有覆盖器件上的焊盘（14）的UBM的第一锡层（40）。第一锡层与UBM中的金属层（36）反应以形成金属间化合物，用于将焊料凸块粘合到焊盘上。厚的引线层（42）覆盖在第一锡层上，以提供焊料凸点的实质部件。第二锡层（44）覆盖引线层，以在回流期间在凸块的顶表面处提供局部共晶形成。具有至少该焊料凸块结构的器件可以直接附着在陶瓷或PC板基板上。锡和/或铅的附加层可以补充到基本凸块结构以优化共晶形成速率。

2. 发明授权

US4602271A Personalizable masterslice substrate for semiconductor chips 失效
标题翻译：用于半导体芯片的个性化主板基板
公开(公告)号：US4602271A
公开(公告)日：1986-07-22
申请号：US682963
申请日：1984-02-15
申请人： William E. Dougherty, Jr. , Stuart E. Greer , William J. Nestork , William T. Norris
发明人： William E. Dougherty, Jr. , Stuart E. Greer , William J. Nestork , William T. Norris
IPC分类号： H01L23/538 , H01L39/04 , H01L23/02 , H01L23/08
CPC分类号： H01L23/5385 , H01L2924/0002 , H01L2924/15174
摘要： A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.
摘要翻译：提供用于封装半导体芯片的基板，其由相对端部终止于安装表面的导体和在表面下方延伸的中间部分构成。导体的端部以沿着基板纵向重复的图案布置，由不具有导体端的正交条分开，以允许密集的表面布线。重复图案被布置成允许具有足够间隔的芯片安装位置以允许表面布线。以这种方式，可以通过个性化表面布线和预置的基板导体连接相同和重复图案的芯片。

3. 发明授权

US06713381B2 Method of forming semiconductor device including interconnect barrier layers 失效
标题翻译：形成包括互连阻挡层的半导体器件的方法
公开(公告)号：US06713381B2
公开(公告)日：2004-03-30
申请号：US10051262
申请日：2002-01-18
申请人： Alexander L. Barr , Suresh Venkatesan , David B. Clegg , Rebecca G. Cole , Olubunmi Adetutu , Stuart E. Greer , Brian G. Anthony , Ramnath Venkatraman , Gregor Braeckelmann , Douglas M. Reber , Stephen R. Crown
发明人： Alexander L. Barr , Suresh Venkatesan , David B. Clegg , Rebecca G. Cole , Olubunmi Adetutu , Stuart E. Greer , Brian G. Anthony , Ramnath Venkatraman , Gregor Braeckelmann , Douglas M. Reber , Stephen R. Crown
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L21/76843 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2223/54473 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05025 , H01L2224/05027 , H01L2224/0508 , H01L2224/05147 , H01L2224/05157 , H01L2224/05166 , H01L2224/05172 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05572 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/12042 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2924/013 , H01L2924/0496 , H01L2924/0539 , H01L2924/0538 , H01L2924/0537
摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
摘要翻译：互连覆盖半导体器件衬底（10）。在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

4. 发明授权

US5468655A Method for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modules 失效
标题翻译：使用包含球形模块的金属膏在半导体管芯和衬底之间形成临时附着的方法
公开(公告)号：US5468655A
公开(公告)日：1995-11-21
申请号：US332311
申请日：1994-10-31
申请人： Stuart E. Greer
发明人： Stuart E. Greer
IPC分类号： G01R1/073 , G01R31/28 , H01L21/68 , H05K3/34 , H01L21/283 , H01L21/58 , H01L21/60 , H01L21/66
CPC分类号： H05K3/3436 , G01R1/07314 , H01L21/6835 , G01R31/2831 , G01R31/2886 , H05K2201/10992 , H05K2203/041 , H05K2203/162 , H05K3/3463 , H05K3/3484 , Y02P70/613 , Y10T29/49004
摘要： A nodular metal paste (42) is used to temporarily attach the bumps (34) on a semiconductor die (32) to a substrate (38). The spherical nodules (44) composing the metal paste are dispensed onto contact pads (40) on the substrate, and then heated until they partially melt. The partial liquid region permits bonding of the individual metal nodules to the contact pads and to adjacent nodules. Subsequently, a bumped die is placed over the nodules and heated to a minimum temperature required to partially remelt to form a local tack joint. Because the metallurgical contact area between the paste nodules and the bumps is minimized, electrical contact can be sustained with a small cross-sectional area of connected material to create an electrically sound but physically weak link between die and the substrate. Once connected to the substrate, the die may be tested and burned-in, and removed afterwards with little damage to the bumps.
摘要翻译：使用球状金属膏（42）将半导体管芯（32）上的凸块（34）临时固定到基板（38）上。将组成金属糊的球形结节（44）分配到基底上的接触垫（40）上，然后加热直到它们部分熔化。部分液体区域允许将各个金属结节结合到接触垫和相邻的结节。随后，将凸起的模具放置在结节上并加热至部分重熔所需的最低温度以形成局部粘性接头。由于粘结结块和凸块之间的冶金接触面积最小化，所以可以用连接材料的小横截面面积来维持电接触，从而在管芯和衬底之间产生电声但物理上的弱连接。一旦连接到基板上，可以对模具进行测试和烧录，并且之后被去除，几乎不会损坏凸块。

5. 发明授权

US4598470A Method for providing improved electrical and mechanical connection between I/O pin and transverse via substrate 失效
标题翻译：用于在I / O引脚和横向通孔基板之间提供改进的电气和机械连接的方法
公开(公告)号：US4598470A
公开(公告)日：1986-07-08
申请号：US713569
申请日：1985-03-18
申请人： William E. Dougherty, Jr. , Stuart E. Greer , Robert W. Sargent
发明人： William E. Dougherty, Jr. , Stuart E. Greer , Robert W. Sargent
IPC分类号： H01R43/20 , H05K1/03 , H05K3/30 , H05K3/32
CPC分类号： H05K3/32 , H01R43/205 , H05K3/308 , H05K1/0306 , H05K2201/09854 , H05K2201/10303 , H05K2201/1059 , H05K2203/1189 , Y10T29/4913 , Y10T29/49139
摘要： A method of making an aperture of a predetermined shape into a dielectric substrate which will lockingly receive a deformable contact pin. It includes providing a dielectric material which shrinks in response to a heat treatment by an amount which is different in one direction from that in another direction, and which irreversibly changes dimensions in its two orthogonal directions in proportion to this difference. An aperture is formed in such a material, in a direction normal to the plane of the two orthogonal directions and the material is subjected to a heat treatment that causes a differential shrinkage in the aperture and a change in the shape of the aperture. A deformable contact pin is then forced into a locking position in the aperture. By using such a method to lock a contact pin in close proximity to a conductive line extending across the substrate or by having the aperture and the pin extend through the substrate, electrical circuits on one side of the substrate can be contacted through a contact pin on the opposite side of the substrate.
摘要翻译：将预定形状的孔径制造成将锁定地容纳可变形接触销的电介质基片的方法。它包括提供一种电介质材料，该电介质材料响应于热处理而收缩的量在一个方向上与另一个方向上的量不同，并且在该两个正交方向上不均匀地改变尺寸与该差异成比例。在这样的材料中，沿垂直于两个正交方向的平面的方向形成孔，并且材料经受热处理，导致孔径不均匀收缩和孔的形状变化。然后可变形接触销被迫进入孔中的锁定位置。通过使用这种方法来将接触销锁紧在延伸穿过衬底的导电线附近，或者通过使孔和引脚延伸穿过衬底，衬底一侧上的电路可以通过接触引脚衬底的相对侧。

6. 发明授权

US06451681B1 Method of forming copper interconnection utilizing aluminum capping film 有权
标题翻译：使用铝封盖膜形成铜互连的方法
公开(公告)号：US06451681B1
公开(公告)日：2002-09-17
申请号：US09411266
申请日：1999-10-04
申请人： Stuart E. Greer
发明人： Stuart E. Greer
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L23/5256 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05018 , H01L2224/05558 , H01L2224/05562 , H01L2224/05624 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/48463 , H01L2224/85399 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01016 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2224/45099 , H01L2924/01082 , H01L2224/05552
摘要： A mostly copper-containing interconnect (126) overlies a semiconductor device substrate (100), and a transitional metallurgy structure (312, 508, 716, 806) that includes an aluminum-containing film (200, 506, 702, 802) contacts a portion of the mostly copper-containing interconnect. In one embodiment, the transitional metallurgy is formed over a portion of a bond pad (128). In an alternative embodiment, the transitional metallurgy includes an energy alterable fuse portion (710) that electrically contacts two conductive regions (712 and 714), and in yet another embodiment, the transitional metallurgy is formed over a copper-containing edge seal portion (809).
摘要翻译：主要是含铜的互连（126）覆盖半导体器件衬底（100），并且包括含铝膜（200,506,702,802）的过渡冶金结构（312,508,716,806）接触一个主要是含铜互连的部分。在一个实施例中，过渡冶金形成在接合焊盘（128）的一部分上。在替代实施例中，过渡冶金包括电接触两个导电区域（712和714）的能量可变的熔断器部分（710），并且在另一个实施例中，过渡冶金形成在含铜边缘密封部分（809））。

7. 发明授权

US5597737A Method for testing and burning-in a semiconductor wafer 失效
标题翻译：测试和燃烧半导体晶圆的方法
公开(公告)号：US5597737A
公开(公告)日：1997-01-28
申请号：US552448
申请日：1995-11-03
申请人： Stuart E. Greer , Joel P. Dietz , Aubrey K. Sparkman
发明人： Stuart E. Greer , Joel P. Dietz , Aubrey K. Sparkman
IPC分类号： G01R1/067 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2831 , G01R31/2886
摘要： Flip-chip is fast becoming the mounting method of choice in the semiconductor industry for dice having a high number of contacts. Since many applications require known-good-die, these flip-chip semiconductor dice must be tested and burned-in. By testing and burning-in the semiconductor wafers prior to solder bumping, the probe tips (42, 44, 46 & 48) can contact the hard planar surface of the under-bump-metallurgy (40) on each bonding pad (14) for easier and more reliable contact and hence test results. The probe tips can be either of an array (42 & 44) or cantilevered needle (46 & 48) type. Blunt probe tips (42 & 48) are well-suited to making contact on the shoulder of each bonding pad of each semiconductor die, while sharp probe tips (44 & 46) are preferable for contacting the center of each bonding pad. Solder bumping is performed post-testing.
摘要翻译：倒装芯片正在快速成为半导体工业中具有大量接触的骰子的安装方法。由于许多应用需要已知的裸芯片，因此这些倒装芯片半导体芯片必须经过测试和烧录。通过在焊料凸起之前测试和燃烧半导体晶片，探针尖端（42,44,46和48）可接触每个接合焊盘（14）上的凸点下 - 冶金学（40）的硬平坦表面，用于更容易和更可靠的接触和因此的测试结果。探针尖端可以是阵列（42和44）或悬臂针（46和48）类型。钝头探针尖端（42和48）非常适合于在每个半导体管芯的每个焊盘的肩部上接触，而尖锐的探针尖端（44和46）优选用于接触每个焊盘的中心。焊接碰撞在测试后进行。

8. 发明授权

US5104695A Method and apparatus for vapor deposition of material onto a substrate 失效
标题翻译：用于将材料蒸发沉积到基材上的方法和装置
公开(公告)号：US5104695A
公开(公告)日：1992-04-14
申请号：US404803
申请日：1989-09-08
申请人： Stuart E. Greer , Eric E. Millham , Adolf E. Wirsing
发明人： Stuart E. Greer , Eric E. Millham , Adolf E. Wirsing
IPC分类号： C23C14/24
CPC分类号： C23C14/243
摘要： A method and apparatus for depositing the material onto a substrate is provided. The apparatus includes a mesh member which has impregnated therein the material which is to be vapor deposited. The mesh member with the material thereon is heated to vaporize the material and the vaporized material is then deposited onto the desired substrate. Preferably the material that is deposited is maintained in a crucible having an opening and the mesh member is disposed over the opening. The material in the crucible is vaporized and condensed onto the mesh member, and the condensed material wicks through the mesh member and then revaporizes from the top of the mesh member and is deposited onto the substrates.

9. 发明授权

US4202007A Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers 失效
标题翻译：具有内部导体图案的多层电介质平面结构，其特征在于设置在层的公共边缘表面处的相对端子
公开(公告)号：US4202007A
公开(公告)日：1980-05-06
申请号：US918213
申请日：1978-06-23
申请人： William E. Dougherty , Stuart E. Greer
发明人： William E. Dougherty , Stuart E. Greer
IPC分类号： H05K3/46 , H01L23/498 , H01L23/538 , H05K1/00 , H01L39/02 , H01L23/48 , H01L29/44
CPC分类号： H01L23/5383 , H01L23/49822 , H05K1/0298 , H01L2924/09701 , H01L2924/15174 , H01L2924/15192 , H01L2924/15312 , H01L2924/3011
摘要： The coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering, with the edge side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The conductor runs are returned through the body to the active face of the body to position the opposite or distal ends of the conductors thereat, in an increased spaced relationship of the distal conductor terminations. For external connection, terminal pins may be embedded in the fired body for connection at adjacent and to the distal conductor termination, with the pins projecting therefrom.
摘要翻译：将电介质生片上的导体图案涂覆到其公共边缘上，其中堆叠或叠加多个片材以包围导体图案，随后烧结，其中具有暴露端端的烧制体的边缘侧变为实际电路中连接有半导体器件的主体的表面，其中导线连接到相应的公共末端。导体延伸通过主体返回到主体的主动面，以将导体的相对或远端定位在远端导体终端的增加的间隔关系中。对于外部连接，端子引脚可以嵌入在烧制体中，用于在相邻端和远端导体端子处连接，其中引脚从其突出。

10. 发明授权

US06689680B2 Semiconductor device and method of formation 有权
公开(公告)号：US06689680B2
公开(公告)日：2004-02-10
申请号：US09905756
申请日：2001-07-14
申请人： Stuart E. Greer
发明人： Stuart E. Greer
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L23/3192 , H01L2224/0401 , H01L2224/05018 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05557 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/13022 , H01L2224/13099 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy (414) is formed over a semiconductor bond pad (128), wherein the underbump metallurgy (414) comprises a chromium, copper, and nickel phased-region (404), and wherein the presence of nickel in the phased-region (404) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu6Sn5 copper-tin intermetallics.

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