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1. 发明授权

US07465986B2 Power semiconductor device including insulated source electrodes inside trenches 有权
标题翻译：功率半导体器件包括沟槽内的绝缘源电极
公开(公告)号：US07465986B2
公开(公告)日：2008-12-16
申请号：US11211268
申请日：2005-08-25
申请人： Dev Alok Girdhar , Ling Ma , Steven T. Peake , David Paul Jones
发明人： Dev Alok Girdhar , Ling Ma , Steven T. Peake , David Paul Jones
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/7805 , H01L29/7806 , H01L29/861
摘要： A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.
摘要翻译：功率半导体器件包括形成在半导体本体内的多个沟槽，每个沟槽包括形成在其中的一个或多个电极。具体地，根据本发明的实施例，半导体器件的多个沟槽可以包括一个或多个栅电极，可以包括一个或多个栅电极或一个或多个源电极，或者可以包括栅极和源极的组合电极形成在其中。沟槽和电极在半导体本体内可能具有不同的深度。

2. 发明授权

US07232726B2 Trench-gate semiconductor device and method of manufacturing 失效
标题翻译：沟槽栅极半导体器件及其制造方法
公开(公告)号：US07232726B2
公开(公告)日：2007-06-19
申请号：US10515749
申请日：2003-05-21
申请人： Steven T. Peake , Philip Rutter
发明人： Steven T. Peake , Philip Rutter
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/4238 , H01L29/66674 , H01L29/7397 , H01L29/7801 , H01L29/7827 , H01L2224/05554 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171
摘要： Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove into the semiconductor body for receiving the gate, and etching a second groove into the top major surface of the semiconductor body, the second groove extending from the first groove and being narrower than the first groove. The invention enables better control of the vertical extent of the gate below the top major surface of the semiconductor body.
摘要翻译：与示例性实施例一致，使用具有改进的再现性的工艺制造具有设置在沟槽栅极下方的场板的沟槽栅极半导体器件，例如MOSFET或IGBT。该方法包括以下步骤：将第一沟槽蚀刻到用于接收栅极的半导体本体中，并且将第二沟槽蚀刻到半导体主体的顶部主表面中，第二凹槽从第一凹槽延伸并且比第一凹槽更窄。本发明能够更好地控制栅极在半导体主体的顶部主表面下方的垂直范围。

3. 发明授权

US07122860B2 Trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件
公开(公告)号：US07122860B2
公开(公告)日：2006-10-17
申请号：US10515748
申请日：2003-05-21
申请人： Steven T. Peake , Philip Rutter , Raymond J. Grover
发明人： Steven T. Peake , Philip Rutter , Raymond J. Grover
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/16 , H01L29/407 , H01L29/4232 , H01L29/7397 , H01L29/7825 , H01L29/7828 , H01L2224/05599 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/19041 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A trench-gate semiconductor device, for example a MOSFET or IGBT, includes a semiconductor body (20) having a drain region (4) comprising a drain drift region (4a) and a drain contact region (4b). An insulated field plate (24) is included in the trench (10) between the gate (8) and the drain contact region (4b), wherein the field plate (24) is for connection to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region (4a). The field plate (24) causes the potential drop across the drain drift region (4a) to be spread considerably more evenly, particularly at applied voltages greater than the bulk breakdown voltage, thereby substantially increasing the breakdown voltage of the device.
摘要翻译：沟槽栅半导体器件，例如MOSFET或IGBT，包括具有包括漏极漂移区（4a）和漏极接触区（4b）的漏极区（4）的半导体本体（20）。绝缘场板（24）包括在栅极（8）和漏极接触区域（4b）之间的沟槽（10）中，其中场板（24）用于连接到大于栅极电位的偏置电位并且接近漏极漂移区域（4a）的体积击穿电压。场板（24）导致穿过漏极漂移区域（4a）的电位降明显地更均匀地扩散，特别是在大于体击穿电压的施加电压下，从而显着增加了器件的击穿电压。

4. 发明授权

US07122433B2 Method for manufacturing trench gate semiconductor device 失效
标题翻译：沟槽栅极半导体器件的制造方法
公开(公告)号：US07122433B2
公开(公告)日：2006-10-17
申请号：US10821904
申请日：2004-04-09
申请人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
发明人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/42372 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7811 , H01L2924/13055 , H01L2924/13091 , H01L2924/30105
摘要： A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e). The lateral extent of the conductive layer (11c) terminates in an edge (11a,11b) that is defined on the trench-etch mask (51).
摘要翻译：为蜂窝状沟槽栅极半导体器件（例如功率MOSFET）中的至少一组电池提供器件端接结构和/或栅极汇流条结构和/或其它端部结构。在该端部结构中，例如多晶硅栅极材料的导电层（11c）在中间绝缘层（55）上延伸穿过沟道容纳区域（15）的较高掺杂（P +）端部区域（150））。该绝缘层（55）包括沟槽蚀刻掩模（51）的优选地包括氮化硅的区域（51e），其厚度大于栅极电介质层（17）的厚度。窗口（51a）在端部沟槽（20e）延伸到P +区域（150）的位置处延伸穿过沟槽蚀刻掩模（51）。端部沟槽（20e）是绝缘栅极沟槽（20）延伸到P +区域（150）中并且容纳沟槽栅极（11）的延伸部分（11e）的延伸。导电层（11c）经由窗口（51e）连接到沟槽栅延伸部（11e）。导电层（11c）的横向范围终止于限定在沟槽蚀刻掩模（51）上的边缘（11a，11b）。

5. 发明授权

US06800900B2 Trench-gate semiconductor devices and their manufacture 有权
标题翻译：沟槽门半导体器件及其制造
公开(公告)号：US06800900B2
公开(公告)日：2004-10-05
申请号：US10213460
申请日：2002-08-06
申请人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
发明人： Steven T. Peake , Georgios Petkos , Philip Rutter , Raymond J. Grover
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/42372 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7811 , H01L2924/13055 , H01L2924/13091 , H01L2924/30105
摘要： A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e). The lateral extent of the conductive layer (11c) terminates in an edge (11a,11b) that is defined on the trench-etch mask (51).
摘要翻译：为蜂窝状沟槽栅极半导体器件（例如功率MOSFET）中的至少一组电池提供器件端接结构和/或栅极汇流条结构和/或其它端部结构。在该端部结构中，例如多晶硅栅极材料的导电层（11c）在通道容纳区域（15）的较高掺杂（P +）端部区域（150）上的中间绝缘层（55）上延伸，。该绝缘层（55）包括沟槽蚀刻掩模（51）的优选地包括氮化硅的区域（51e），其厚度大于栅极电介质层（17）的厚度。窗口（51a）在端部沟槽（20e）延伸到P +区域（150）的位置处延伸穿过沟槽蚀刻掩模（51）。端部沟槽（20e）是绝缘栅极沟槽（20）延伸到P +区域（150）中并且容纳沟槽栅极（11）的延伸部分（11e）的延伸。导电层（11c）经由窗口（51e）连接到沟槽栅延伸部（11e）。导电层（11c）的横向延伸终止在限定在沟槽蚀刻掩模（51）上的边缘（11a，11b）中。

6. 发明授权

US06780722B2 Field effect transistor on insulating layer and manufacturing method 有权
标题翻译：场效应晶体管在绝缘层上的制造方法
公开(公告)号：US06780722B2
公开(公告)日：2004-08-24
申请号：US10265579
申请日：2002-10-07
申请人： Steven T. Peake
发明人： Steven T. Peake
IPC分类号： H01L21336
CPC分类号： H01L29/66681 , H01L29/1095 , H01L29/66674 , H01L29/7824
摘要： A field effect transistor has source 12, body 10 and drain 8 formed on an insulating layer 4. Implant regions 40 are implanted under the source 12, laterally aligned with the source 12 by implantation through opening in the source mask. The ruggedness of the transistor may thereby be improved without affecting the doping in channel region 19.
摘要翻译：场效应晶体管具有形成在绝缘层4上的源极12，主体10和漏极8.植入区域40通过在源极掩模中的开口进行注入而植入在源极12下方与源极12对准。因此可以改善晶体管的粗糙度，而不影响沟道区域19中的掺杂。

7. 发明授权

US06677642B2 Field effect transistor structure and method of manufacture 有权
标题翻译：场效应晶体管结构及制造方法
公开(公告)号：US06677642B2
公开(公告)日：2004-01-13
申请号：US10099683
申请日：2002-03-15
申请人： Steven T. Peake , Raymond J. Grover
发明人： Steven T. Peake , Raymond J. Grover
IPC分类号： H01L2976
CPC分类号： H01L29/404 , H01L21/266 , H01L27/0255 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/42368 , H01L29/4983 , H01L29/66681 , H01L29/7821 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor structure is formed with a body semiconductor layer (5) having source (9), body (7), drift region and drain (11). An upper semiconductor layer (21) is separated from the body by an oxide layer (17). The upper semiconductor layer (21) is doped to have a gate region (23) arranged over the body (7), a field plate region (25) arranged over the drift region 13 and at least one p-n junction (26) forming at least one diode between the field plate region (25) and the gate region (23). A source contact (39) is connected to both the source (9) and the field plate region (25).
摘要翻译：场效应晶体管结构形成有具有源极（9），主体（7），漂移区域和漏极（11）的主体半导体层（5）。上半导体层（21）通过氧化物层（17）与主体分离。上半导体层（21）被掺杂以具有布置在主体（7）上的栅极区（23），布置在漂移区13上的场板区（25）和至少形成至少一个pn结（26）在场板区域（25）和栅极区域（23）之间的一个二极管。源极接触（39）连接到源极（9）和场板区域（25）。

8. 发明授权

US06566708B1 Trench-gate field-effect transistors with low gate-drain capacitance and their manufacture 有权
标题翻译：具有低栅极 - 漏极电容的沟槽栅极场效应晶体管及其制造
公开(公告)号：US06566708B1
公开(公告)日：2003-05-20
申请号：US09993201
申请日：2001-11-16
申请人： Raymond J. Grover , Steven T. Peake
发明人： Raymond J. Grover , Steven T. Peake
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4916 , H01L29/7397
摘要： Trench-gate field-effect transistors, for example power MOSFETs, are disclosed having trenched electrode configurations (11,23) that permit fast switching of the transistor, while also providing over-voltage protection for the gate dielectric (21) and facilitating manufacture. The gate electrode (11) comprising a semiconductor material of one conductivity type (n) is present in an upper part of a deeper insulated trench (20,21) that extends into a drain region (14,14a) of the transistor. A lower electrode (23) connected to a source (13,33) of the transistor is present in the lower part of the trench. This lower electrode (23) comprises a semiconductor material of opposite conductivity type (p) that adjoins the semiconductor material of the gate electrode (11) to form a p-n junction (31) between the gate electrode (11) and the lower electrode (23). The p-n junction (31) provides a protection diode (D) between the gate electrode (11) and the source (13,33). The gate electrode (11) is shielded from most of the drain region by the lower electrode (23), so reducing the gate-drain capacitance and improving the switching speed of the transistor.
摘要翻译：公开了沟槽栅场效应晶体管，例如功率MOSFET，其具有允许晶体管快速切换的沟槽电极配置（11,23），同时还为栅极电介质（21）提供过电压保护并且有利于制造。包含一种导电类型（n）的半导体材料的栅电极（11）存在于延伸到晶体管的漏区（14,14a）的较深绝缘沟槽（20,21）的上部。连接到晶体管的源极（13,33）的下电极（23）存在于沟槽的下部。该下电极（23）包括与栅电极（11）的半导体材料邻接以形成栅极（11）和下电极（23）之间的pn结（31）的相反导电型（p）的半导体材料）。 p-n结（31）在栅电极（11）和源极（13,33）之间提供保护二极管（D）。栅电极（11）通过下电极（23）与大部分漏极区域屏蔽，因此降低栅 - 漏电容并提高晶体管的开关速度。

9. 发明授权

US07642596B2 Insulated gate field effect transistor 失效
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US07642596B2
公开(公告)日：2010-01-05
申请号：US10578286
申请日：2004-11-03
申请人： Steven T. Peake
发明人： Steven T. Peake
IPC分类号： H01L29/78 , H01L29/41 , H01L29/739
CPC分类号： H01L29/7802 , H01L29/402 , H01L29/407 , H01L29/7395
摘要： An insulated gate field effect transistor has a drain region (2,4), a body region (6) of opposite conductivity type and a source region (8) and an insulated gate (14) extending laterally over the body region (6), defining a channel region (30) extending in the body region (6) from a source end adjacent to the source region (8) to a drain end adjacent to a drain end part (26) of the drain region (4). A conductive shield plate (22) is provided adjacent to the drain end for shielding the gate. Embodiments include a shield plate extension (32) extending over the drain region from the shield plate (22) towards the gate (14).
摘要翻译：绝缘栅场效应晶体管具有漏极区域（2,4），具有相反导电类型的体区域（6）和源区域（8）以及在身体区域（6）上横向延伸的绝缘栅极（14）限定从所述源区域（8）的源极端部延伸到所述体区（6）中的沟道区域（30）到与所述漏极区域（4）的漏极端部（26）相邻的漏极端。导电屏蔽板（22）邻近漏极端设置，用于屏蔽栅极。实施例包括从屏蔽板（22）朝向门（14）在漏极区域上延伸的屏蔽板延伸部（32）。

10. 发明授权

US07504690B2 Power semiconductor devices 有权
标题翻译：功率半导体器件
公开(公告)号：US07504690B2
公开(公告)日：2009-03-17
申请号：US10529731
申请日：2003-09-15
申请人： Brendan P. Kelly , Steven T. Peake , Raymond J. Grover
发明人： Brendan P. Kelly , Steven T. Peake , Raymond J. Grover
IPC分类号： H01L29/72
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/7397 , H01L29/7831 , H02M3/1588 , H03K17/063 , Y02B70/1466
摘要： A vertical insulated gate field effect power transistor (3) has a plurality of parallel transistor cells (TC3) with a peripheral gate structure (G31, G2) at the boundary between each two transistor cells (TC3). The gate structure (G31, G32) comprises first (G31) and second (G32) gates isolated from each other so as to be independently operable. The first gate (G31) is a trench-gate (21, 22), and the second gate (G32) has at least an insulated planar gate portion (13, 14). Simultaneous operation of the first (G31) and second (G32) gates forms a conduction channel (23c, 23b) between source (16) and drain (12) regions of the device (3). The device (3) has on-state resistance approaching that of a trench-gate device, better switching performance than a DMOS device, and a better safe operating area than a trench-gate device. The device (3) may be a high side power transistor is series with a low side power transistor (6) in a circuit arrangement (50) (FIG. 14) for supplying a regulated output voltage. The device (3) may also be a switch in a circuit arrangement (60) (FIG. 15) for supplying current to a load (L). These circuit arrangements (50, 60) include a terminal (Vcc, VF) for applying a supplied fixed potential to an electrode (G311) for the first gates (G31) and a gate driver circuit (573, 673) for applying modulating potential to an electrode (G321) for the second gates (G32).
摘要翻译：垂直绝缘栅场效应功率晶体管（3）在每两个晶体管单元（TC3）之间的边界处具有多个具有外围栅极结构（G31，G2）的并联晶体管单元（TC3）。栅极结构（G31，G32）包括彼此隔离的第一（G31）和第二（G32）栅极，以便可独立地操作。第一栅极（G31）是沟槽栅极（21,22），第二栅极（G32）至少具有绝缘平面栅极部分（13,14）。第一（G31）和第二（G32）栅极的同时操作在器件（3）的源极（16）和漏极（12）区域之间形成导电沟道（23c，23b）。器件（3）具有接近沟槽栅极器件的导通电阻，比DMOS器件更好的开关性能，以及比沟槽栅极器件更好的安全工作区域。装置（3）可以是用于提供稳定输出电压的电路装置（50）（图14）中的与低侧功率晶体管（6）串联的高侧功率晶体管。装置（3）还可以是用于向负载（L）供电的电路装置（60）（图15）中的开关。这些电路装置（50,60）包括用于将提供的固定电位施加到用于第一栅极（G31）的电极（G311）的端子（Vcc，VF）和用于施加调制电位的栅极驱动电路（573,673）用于第二栅极（G32）的电极（G321）。

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