专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06438710B1 Circuit and method for improving memory integrity in a microprocessor based application 有权
标题翻译：用于提高基于微处理器的应用中的存储器完整性的电路和方法
公开(公告)号：US06438710B1
公开(公告)日：2002-08-20
申请号：US09386794
申请日：1999-08-31
申请人： James P. Walsh , Steven T. Delong
发明人： James P. Walsh , Steven T. Delong
IPC分类号： G06F1100
CPC分类号： G06F11/1441 , G06F11/0757 , H04M3/523
摘要： A microprocessor based system such as an automatic call distributor having a reset circuit to improve memory integrity of electronic memory is disclosed. The reset circuit includes a reset controller which receives an external reset signal that can be generated from a number of different sources. The external resent signal is synchronized with activity on a bus to produce an internal reset signal which is applied to the microprocessor to reset it after all pending requests for bus access are completed. The microprocessor is then reset, thus improving integrity of electronic memory.
摘要翻译：公开了一种基于微处理器的系统，例如具有用于提高电子存储器的存储器完整性的复位电路的自动呼叫分配器。复位电路包括复位控制器，其接收可以从多个不同的源产生的外部复位信号。外部重发信号与总线上的活动同步，以产生内部复位信号，该内部复位信号在完成所有未完成的总线访问请求之后应用于微处理器进行复位。然后微处理器被复位，从而提高电子存储器的完整性。

2. 发明授权

US5140611A Pulse width modulated self-clocking and self-synchronizing data transmission and method for a telephonic communication network switching system 失效
标题翻译：用于电话通信网络交换系统的脉宽调制自时钟和自同步数据传输和方法
公开(公告)号：US5140611A
公开(公告)日：1992-08-18
申请号：US416077
申请日：1989-09-29
申请人： Barry W. Jones , Steven T. DeLong
发明人： Barry W. Jones , Steven T. DeLong
IPC分类号： H03K7/08 , H03K9/08 , H04L7/06 , H04L25/49
CPC分类号： H04L25/4904 , H03K7/08 , H03K9/08 , H04L25/4902 , H04L7/06
摘要： Transmissions of synchronous digital data from a master control unit (50A) to a slave, network termination unit (50B) are via a pulse width modulated data stream including pulse width modulated binary code pulses (20, 22) with a pulse width modulated synchronization pulse (24) all of which have a preselected leading edge transition (28) at the same point in each cycle of a master clock signal. A clock signal is derived at the network termination unit (50B) from the received pulse width modulated binary data stream for decoding and for nonself-clocking, synchronous transmissions from the slave, network termination unit (50B) to the master, control unit (50A). The phase synchronization pulse (24) is employed to maintain phase sychronization between the transmission to and from the control unit (50A).
摘要翻译：网络终端单元（50B）的同步数字数据从主控单元（50A）传输到脉冲宽度调制数据流，脉冲宽度调制二进制码脉冲（20,22）具有脉宽调制同步脉冲（24），它们都在主时钟信号的每个周期的相同点处具有预选的前沿转变（28）。在接收到的用于解码的脉冲宽度调制二进制数据流和从从机，网络终端单元（50B）到主机，控制单元（50A）的非时钟同步传输中，在网络终端单元（50B）处导出时钟信号）。采用相位同步脉冲（24）来保持与控制单元（50A）的传输之间的相位同步。

3. 发明授权

US08081639B2 Method and apparatus for supporting client data transport with timing transparency 有权
标题翻译：用于支持具有定时透明度的客户端数据传输的方法和装置
公开(公告)号：US08081639B2
公开(公告)日：2011-12-20
申请号：US12583267
申请日：2009-08-18
申请人： Lawrence D. Weizeorick , Bruce R. Zelle , Steven T. DeLong
发明人： Lawrence D. Weizeorick , Bruce R. Zelle , Steven T. DeLong
IPC分类号： H04L12/28 , H04J3/06
CPC分类号： G06F1/14 , H04J3/062
摘要： Clock recovery is used in a variety of communications network applications to enable nodes using different clocks to operate in an effectively synchronized manner. Example embodiments of the present invention include an apparatus and corresponding method for supporting client data transport with timing transparency and require neither a common clock to be available at both the ingress and egress sides of the connection nor overhead bytes to recover a client clock. Rather, client traffic clock recovery may be performed in example embodiments of the present invention entirely in the egress data path using the client data received from the ingress side after removing the clients signal from a higher level carrier signal.
摘要翻译：在各种通信网络应用中使用时钟恢复，以使得使用不同时钟的节点能够以有效的同步方式工作。本发明的示例实施例包括一种用于支持具有定时透明度的客户端数据传输的装置和相应方法，并且不需要在连接的入口和出口侧都可以使用公共时钟，也不需要开销字节来恢复客户端时钟。相反，客户端业务时钟恢复可以在本发明的示例实施例中完全在出口数据路径中使用在从更高级别的载波信号中移除客户端信号之后从入口侧接收的客户端数据。

4. 发明申请

US20100192003A1 Method and apparatus for supporting client data transport with timing transparency 有权
标题翻译：用于支持具有定时透明度的客户端数据传输的方法和装置
公开(公告)号：US20100192003A1
公开(公告)日：2010-07-29
申请号：US12583267
申请日：2009-08-18
申请人： Lawrence D. Weizeorick , Bruce R. Zelle , Steven T. DeLong
发明人： Lawrence D. Weizeorick , Bruce R. Zelle , Steven T. DeLong
IPC分类号： G06F1/14
CPC分类号： G06F1/14 , H04J3/062
摘要： Clock recovery is used in a variety of communications network applications to enable nodes using different clocks to operate in an effectively synchronized manner. Example embodiments of the present invention include an apparatus and corresponding method for supporting client data transport with timing transparency and require neither a common clock to be available at both the ingress and egress sides of the connection nor overhead bytes to recover a client clock. Rather, client traffic clock recovery may be performed in example embodiments of the present invention entirely in the egress data path using the client data received from the ingress side after removing the clients signal from a higher level carrier signal.
摘要翻译：在各种通信网络应用中使用时钟恢复，以使得使用不同时钟的节点能够以有效的同步方式工作。本发明的示例实施例包括一种用于支持具有定时透明度的客户端数据传输的装置和相应方法，并且不需要在连接的入口和出口侧都可以使用公共时钟，也不需要开销字节来恢复客户端时钟。相反，客户端业务时钟恢复可以在本发明的示例实施例中完全在出口数据路径中使用在从更高级别的载波信号中移除客户端信号之后从入口侧接收的客户端数据。

5. 发明授权

US06574330B1 Bus interface for automatic call distributor 有权
标题翻译：总线接口，用于自动呼叫分配器
公开(公告)号：US06574330B1
公开(公告)日：2003-06-03
申请号：US09460192
申请日：1999-12-10
申请人： Daniel F. Baker , Paul D. Swardstrom , Steven T. DeLong
发明人： Daniel F. Baker , Paul D. Swardstrom , Steven T. DeLong
IPC分类号： H04M300
CPC分类号： H04M3/523
摘要： An automatic call distribution system includes an automatic call distribution network, a plurality of network terminations interconnectable with the automatic call distribution network using a first bus protocol, and an interface which is interconnectable with one of the first network terminations using the first bus protocol. The interface is operable for interfacing between the first bus protocol and a second bus protocol different than the first bus protocol, and a network termination functional module is interconnectable with the interface using the second bus protocol. An automatic call distributor interconnectable with a network termination using a first bus protocol is used by a method that includes the steps of coupling a bus converter with the network termination using the first bus protocol and coupling a network termination functional module with the bus converter using a second bus protocol different than the first bus protocol. The bus converter is operable for converting between the first bus protocol and the second bus protocol.
摘要翻译：自动呼叫分配系统包括自动呼叫分配网络，使用第一总线协议与自动呼叫分配网络互连的多个网络终端，以及可以使用第一总线协议与第一网络终端之一互连的接口。该接口可操作用于在第一总线协议和不同于第一总线协议的第二总线协议之间进行接口，并且网络终端功能模块可使用第二总线协议与接口互连。使用第一总线协议与网络终端互连的自动呼叫分配器通过一种方法来使用，该方法包括以下步骤：使用第一总线协议将总线转换器与网络终端耦合，并使用总线转换器将网络终端功能模块与总线转换器第二总线协议不同于第一总线协议。总线转换器可操作用于在第一总线协议和第二总线协议之间进行转换。

6. 发明授权

US4881195A Multi-requester arbitration circuit 失效
标题翻译：多请求者仲裁电路
公开(公告)号：US4881195A
公开(公告)日：1989-11-14
申请号：US935421
申请日：1986-11-26
申请人： Steven T. DeLong , James E. Snook
发明人： Steven T. DeLong , James E. Snook
IPC分类号： G06F13/14
CPC分类号： G06F13/14
摘要： A multi-requester arbitration circuit receives multiple asynchronous request signals and provides a first common timing signal from the request signals. A sample-and-hold circuit receives each of the request signals and produces corresponding output sample signals. The sample-and-hold circuit receives the first common timing signals. A time delay circuit produces a second timing signal from the first common timing signal. A storage circuit receives the output sample signals and produces corresponding output stored signals. The storage circuit receives the second timing signal. An arbitration circuit receives the output stored signals to select one of the request signals and provide at least an output control signal indicative thereof. The sample-and-hold circuit samples each of the request signals before the first common timing signals causes the sample-and-hold circuit to hold all request signals. Each of the output sample signals is received by the storage circuit before the second timing signal causes the storage circuit to retain the output storage signals for use by the arbitration circuit.
摘要翻译：多请求者仲裁电路接收多个异步请求信号，并从请求信号提供第一公共定时信号。采样和保持电路接收每个请求信号并产生相应的输出采样信号。采样和保持电路接收第一公共定时信号。时间延迟电路从第一公共定时信号产生第二定时信号。存储电路接收输出采样信号并产生相应的输出存储信号。存储电路接收第二定时信号。仲裁电路接收所输出的存储信号以选择一个请求信号，并提供至少一个指示该请求信号的输出控制信号。采样和保持电路在第一公共定时信号之前对每个请求信号进行采样，使得采样和保持电路保持所有请求信号。在第二定时信号使存储电路保持由仲裁电路使用的输出存储信号之前，存储电路接收每个输出采样信号。

7. 发明授权

US06546023B1 Switch voice/data service extension to remote facilities 有权
标题翻译：将语音/数据服务扩展到远程设施
公开(公告)号：US06546023B1
公开(公告)日：2003-04-08
申请号：US09405585
申请日：1999-09-27
申请人： Barry W. Jones , Steven T. Delong , Jerrold S. Zdenek
发明人： Barry W. Jones , Steven T. Delong , Jerrold S. Zdenek
IPC分类号： H04J316
CPC分类号： H04M3/5125 , H04Q3/0025
摘要： A method and apparatus are provided for exchanging control information and voice data between an automatic call distributor and a line card of the automatic call distributor located at a site remote from the automatic call distributor through a wide-bandwidth communication channel. The method includes the step of allocating at least a first portion of the bandwidth of the wide-bandwidth communication channel for the control information and at least a second portion of the bandwidth to voice data. The interprocessor control information is transceived between a controller of the automatic call distributor and a controller of the line card under a packet data format within the first portion of the bandwidth allocated for control information and the voice data is transceived under a dedicated channel format within the second portion of the bandwidth between the automatic call distributor and line card.
摘要翻译：提供了一种方法和装置，用于通过宽带通信信道在位于远离自动呼叫分配器的位置处的自动呼叫分配器和自动呼叫分配器的线路卡之间交换控制信息和语音数据。该方法包括将用于控制信息的宽带通信信道的带宽的至少第一部分和带宽的至少第二部分分配给语音数据的步骤。处理器控制信息在自动呼叫分配器的控制器和线卡的控制器之间以分组数据格式在分配给控制信息的带宽的第一部分内被收发，并且话音数据以专用信道格式收发自动呼叫分配器和线路卡之间的带宽的第二部分。

8. 发明授权

US5555213A Interface circuit, system and method for interfacing an electronic device and a synchronous state machine having different clock speeds 失效
标题翻译：用于接口电子设备和具有不同时钟速度的同步状态机的接口电路，系统和方法
公开(公告)号：US5555213A
公开(公告)日：1996-09-10
申请号：US496700
申请日：1995-06-29
申请人： Steven T. DeLong
发明人： Steven T. DeLong
IPC分类号： G05B19/042 , G06F5/06 , H03K19/00
CPC分类号： G06F5/06 , G05B19/0423 , G05B2219/25484
摘要： An interface circuit (100) for interfacing an electronic device, such as a microprocessor (102), operating at a device clock speed and a finite synchronous state machine (104) comprised of a D-type flip-flop (106) and a synchronous state machine (108), which are operating at a state clock speed, is provided. The device clock speed being capable of being greater than the state clock speed. The interface circuit.degree. (100) comprises an input circuit, which may comprise a first NAND gate (120), connected to a latch circuit which may comprise interconnected second and third NAND gates (124) and (126). The input circuit and latch circuit store an input signal (121) received from the electronic device and transmit the input signal (121) to the flip-flop (106) when the synchronous state machine (108) is ready to accept further input signals. A system for operating the finite synchronous state machine (104) associated with a state clock speed and a method for interfacing an electronic device operating at a device clock speed and a synchronous state machine (108) operating at a state clock speed are also provided.
摘要翻译：一种接口电路（100），用于接口工作在设备时钟速度的电子设备（例如微处理器）和由D型触发器（106）组成的有限同步状态机（104）提供以状态时钟速度工作的状态机（108）。器件时钟速度能够大于状态时钟速度。接口电路DEG（100）包括输入电路，其可以包括连接到可以包括互连的第二和第三和非门（124）和（126）的锁存电路的第一NAND门（120）。当同步状态机（108）准备好接受进一步的输入信号时，输入电路和锁存电路存储从电子设备接收的输入信号（121）并将输入信号（121）发送到触发器（106）。还提供了一种用于操作与状态时钟速度相关联的有限同步状态机（104）的系统和用于接口以设备时钟速度工作的电子设备和以状态时钟速度操作的同步状态机（108）的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式