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1. 发明授权

US08205066B2 Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor 有权
标题翻译：用于不同扩展指令集的动态配置协处理器，具有专用于应用程序的个人特征，共享存储器存储从主机处理器不可见地分派的指令
公开(公告)号：US08205066B2
公开(公告)日：2012-06-19
申请号：US12263203
申请日：2008-10-31
申请人： Tony Brewer , Steven J. Wallach
发明人： Tony Brewer , Steven J. Wallach
IPC分类号： G06F15/16
CPC分类号： G06F9/30036 , G06F9/30109 , G06F9/3877 , G06F9/3887 , G06F9/3897
摘要： A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.
摘要翻译：提供了一种协处理器，其包括可被动态配置为期望个性的一个或多个应用引擎。例如，应用引擎可以被动态配置为多个不同的向量处理指令集中的任何一个，例如单精度向量处理指令集和双精度向量处理指令集。协处理器还包括在所有不同个性之间共同的公共基础设施，例如指令解码基础设施，存储器管理基础设施，系统接口基础设施和/或标量处理单元（具有基本指令集）。因此，协处理器的个性可以被动态修改（通过重新配置协处理器的一个或多个应用引擎），而协处理器的公共基础设施在各个人物之间保持一致。

2. 发明授权

US08122229B2 Dispatch mechanism for dispatching instructions from a host processor to a co-processor 有权
标题翻译：用于从主处理器向协处理器分派指令的调度机制
公开(公告)号：US08122229B2
公开(公告)日：2012-02-21
申请号：US11854432
申请日：2007-09-12
申请人： Steven J. Wallach , Tony Brewer
发明人： Steven J. Wallach , Tony Brewer
IPC分类号： G06F9/00 , G06F7/44
CPC分类号： G06F9/3877 , G06F9/30185 , G06F9/3802 , G06F9/3879 , G06F9/3897 , G06F12/0855 , G06F12/10 , G06F15/7867
摘要： A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.
摘要翻译：提供了一种调度机制，用于将可执行程序的指令从主处理器分派到异构协处理器。根据某些实施例，在主处理器和异构协处理器之间保持高速缓存一致性，并且利用这种高速缓存一致性来调度由协处理器处理的可执行程序的指令。例如，在某些实施例中，利用指定的存储器部分（例如，“UCB”），其中主处理器可以将信息放置在这样的UCB中，并且协处理器可以从UCB检索信息（反之亦然）。因此，UCB可以用于分派可执行程序的指令以供协处理器处理。在某些实施例中，协处理器可以包括使得协处理器的指令集能够动态改变的动态可重配置逻辑，并且调度操作可以识别要加载到协处理器上的多个预定义指令集中的一个。

3. 发明授权

US4821184A Universal addressing system for a digital data processing system 失效
标题翻译：数字数据处理系统的通用寻址系统
公开(公告)号：US4821184A
公开(公告)日：1989-04-11
申请号：US647272
申请日：1984-09-04
申请人： Gerald F. Clancy , Craig J. Mundie , Stephen I. Schleimer , Steven J. Wallach , Richard G. Bratt
发明人： Gerald F. Clancy , Craig J. Mundie , Stephen I. Schleimer , Steven J. Wallach , Richard G. Bratt
IPC分类号： G06F9/44 , G06F12/00
CPC分类号： G06F9/4428
摘要： A universal addressing system for use in a digital data processing system including a universal memory for storing data including instructions and at least one local system having access to the universal memory. The universal memory is organized into objects, and each item of data is associated with an object. Each object is specified by a unique identifier, and data is addressed by means of a logical address which specifies the UID of the object containing the data and the offset of the data in the object. A processor in the local system responds to instructions by providing memory operation specifiers to the universal memory. Each memory operation specifier specifies a memory operation and a logical address. The offset in the logical address may specify any bit in the object. The memory operation specifier also specifies a length in bits. The universal memory responds to the memory operation specifier by performing the operation specified by the memory operation specifier on the data item beginning at the location specified by the logical address and containing the specified number of bits.
摘要翻译：一种用于数字数据处理系统的通用寻址系统，包括用于存储包括指令的数据的通用存储器和至少一个具有访问通用存储器的本地系统。通用存储器被组织成对象，并且每个数据项与对象相关联。每个对象由唯一的标识符指定，并且数据通过逻辑地址来寻址，该逻辑地址指定包含数据的对象的UID和对象中数据的偏移量。本地系统中的处理器通过向通用存储器提供存储器操作说明符来响应指令。每个存储器操作说明符指定存储器操作和逻辑地址。逻辑地址中的偏移可以指定对象中的任何位。存储器操作说明符还指定长度（以位为单位）。通用存储器通过执行由存储器操作说明符对由逻辑地址指定的位置开始并包含指定位数的数据项指定的操作来响应存储器操作说明符。

4. 发明授权

US4809171A Concurrent processing of data operands 失效
标题翻译：并行处理数据操作数
公开(公告)号：US4809171A
公开(公告)日：1989-02-28
申请号：US147112
申请日：1988-01-21
申请人： Harold W. Dozier , Thomas M. Jones , Steven J. Wallach , Jeffrey H. Gruger
发明人： Harold W. Dozier , Thomas M. Jones , Steven J. Wallach , Jeffrey H. Gruger
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F15/8053 , G06F9/3875 , G06F9/3885
摘要： An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80). The operand processing unit (10) provides concurrent processing of operands to enhance processing speed. The operands and resultants are handled in a manner such that there is a uniform and sequential flow of operands from a source, such as main memory, and a uniform and sequential delivery of resultants to a destination, such as a memory or input/output device.
摘要翻译：操作数处理单元（10）在计算机中执行操作数的处理。单元（10）包括多个操作电路（12,14,16,18,20）。源总线（22）每个时钟周期向操作电路（12,14,16,18,20）提供一个操作数。目的地总线（24）从操作电路（12,14,16,18,20）接收每个时钟周期的一个结果。在每个运算电路中，提供了一个操作数处理电路（80），它用所接收的操作数执行所选择的功能。这些功能包括例如乘法，除法，加法，减法，逻辑与和移位。逻辑电路为操作电路（12,14,16,18,20）提供优先级分配，用于将操作数的加载排序到不处理操作数的最高优先级操作电路（12,14,16,18,20）中在其对应的操作数处理电路（80）内。操作数处理单元（10）提供操作数的并发处理以提高处理速度。操作数和结果以这样的方式处理，使得存在来自源的诸如主存储器的均匀且顺序的操作数流，以及将结果统一并顺序地传递到目的地，诸如存储器或输入/输出设备。

5. 发明授权

US4731734A Digital computer system incorporating object-based addressing and access control and tables defining derivation of addresses of data from operands in instructions 失效
标题翻译：包含基于对象的寻址和访问控制的数字计算机系统和定义从指令中的操作数的地址的地址的表
公开(公告)号：US4731734A
公开(公告)日：1988-03-15
申请号：US830480
申请日：1986-02-14
申请人： Ronald H. Gruner , Gerald F. Clancy , Craig J. Mundie , Stephen I. Schleimer , Steven J. Wallach , Richard G. Bratt , Edward S. Gavrin , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein
发明人： Ronald H. Gruner , Gerald F. Clancy , Craig J. Mundie , Stephen I. Schleimer , Steven J. Wallach , Richard G. Bratt , Edward S. Gavrin , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein
IPC分类号： G06F9/35 , G06F9/44 , G06F9/30
CPC分类号： G06F9/4428 , G06F9/35
摘要： A digital computer system having a memory system organized into objects for storing data and a processor for processing data in response to instructions. An object identifier and an access control list are associated with each object. The memory system responds to logical addresses for data which specify the object containing the data and the offset of the data in the object and to a current subject for which the processor is referencing the data. The memory system performs a memory operation for the processor only if the access control list for the object specified by the logical address allows the current subject to perform the desired memory operation. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions and name tables associated with the procedures. The instructions contain operations codes and names representing data. Each name corresponds to a name table entry in the name table associated with the procedure. The name table for a name contains information from which the processor may derive the logical address for the data represented by the name. The processor may then use the logical address to specify a memory operation on the data represented by the name.
摘要翻译：一种数字计算机系统，具有组织成用于存储数据的对象的存储器系统和用于响应于指令来处理数据的处理器。对象标识符和访问控制列表与每个对象相关联。存储器系统对指定包含数据的对象的数据和对象中的数据的偏移以及处理器正在引用数据的当前对象的数据进行响应。只有当由逻辑地址指定的对象的访问控制列表允许当前主体执行所需的存储器操作时，存储器系统才对处理器执行存储器操作。对象包括过程对象和数据对象。过程对象包含与过程相关联的指令和名称表的过程。指令包含表示数据的操作代码和名称。每个名称对应于与该过程相关联的名称表中的名称表项。名称的名称表包含信息，处理器可从中获取由该名称表示的数据的逻辑地址。然后，处理器可以使用逻辑地址来指定对由该名称表示的数据的存储器操作。

6. 发明授权

US4620275A Computer system 失效
标题翻译：电脑系统
公开(公告)号：US4620275A
公开(公告)日：1986-10-28
申请号：US622451
申请日：1984-06-20
申请人： Steven J. Wallach , Thomas M. Jones , Frank J. Marshall , David A. Nobles , Kent A. Fuka , Steven M. Rowan , William H. Wallace , Harold W. Dozier , David M. Chastain , John W. Clark , Robert B. Kolstad , James E. Mankovich , Michael C. Harris , Jeffrey H. Gruger , Alan D. Gant , Harold D. Shelton , James R. Weatherford , Arthur T. Kimmel , Gary B. Gostin , Gilbert J. Hansen , John M. Golenbieski , Larry W. Spry , Gerald Matulka , Gaynel J. Lockhart , Michael E. Sydow
发明人： Steven J. Wallach , Thomas M. Jones , Frank J. Marshall , David A. Nobles , Kent A. Fuka , Steven M. Rowan , William H. Wallace , Harold W. Dozier , David M. Chastain , John W. Clark , Robert B. Kolstad , James E. Mankovich , Michael C. Harris , Jeffrey H. Gruger , Alan D. Gant , Harold D. Shelton , James R. Weatherford , Arthur T. Kimmel , Gary B. Gostin , Gilbert J. Hansen , John M. Golenbieski , Larry W. Spry , Gerald Matulka , Gaynel J. Lockhart , Michael E. Sydow
IPC分类号： G06F15/78 , G06F9/18
CPC分类号： G06F15/8069
摘要： A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer there is included the logical data cache which stores data at logical addresses such that the central processor can store and retrieve data without the necessity of first making a translation from logical to physical address.
摘要翻译：矢量处理计算机被配置为以流水线方式操作，其中每个功能单元基本上是独立的并且被设计为以最快的方式执行其操作功能。矢量元素通过源总线从存储器，主存储器，物理缓存单元或逻辑高速缓存传送，其中元件被交替地加载到向量处理单元中。矢量控制单元解码矢量指令，并产生用于在矢量处理单元内操作寄存器和逻辑单元的所需控制命令。因此，矢量处理单元基本上并行地工作，使处理速率加倍。所得到的矢量通过目的地总线传送到物理高速缓存单元，主存储器，逻辑高速缓存或输入/输出处理器。在计算机的另一方面，产生了来自商店的入口微词，用于在微指令序列内立即执行第一微指令。剩余的微指令是从常规商店生产的。这减少了第一微指令的检索和执行的延迟。在计算机的另一方面，包括逻辑数据高速缓存，其以逻辑地址存储数据，使得中央处理器可以存储和检索数据，而不需要首先进行从逻辑地址到物理地址的转换。

7. 发明授权

US4532586A Digital data processing system with tripartite description-based addressing multi-level microcode control, and multi-level stacks 失效
标题翻译：数字数据处理系统具有基于三层描述的寻址多级微代码控制和多级堆栈
公开(公告)号：US4532586A
公开(公告)日：1985-07-30
申请号：US266401
申请日：1981-05-22
申请人： Richard G. Bratt , Stephen I. Schleimer , Edward S. Gavrin , John F. Pilat , Steven J. Wallach , Lawrence H. Katz , Douglas M. Wells , Gerald F. Clancy , Craig J. Mundie , David H. Bernstein , Thomas M. Jones , Brett L. Bachman
发明人： Richard G. Bratt , Stephen I. Schleimer , Edward S. Gavrin , John F. Pilat , Steven J. Wallach , Lawrence H. Katz , Douglas M. Wells , Gerald F. Clancy , Craig J. Mundie , David H. Bernstein , Thomas M. Jones , Brett L. Bachman
IPC分类号： G01R31/3185 , G06F7/00 , G06F7/57 , G06F9/22 , G06F9/26 , G06F9/35 , G06F9/44 , G06F9/46 , G06F9/48 , G06F11/07 , G06F12/08 , G06F12/10 , G06F12/14
CPC分类号： G06F9/4428 , G01R31/318505 , G06F11/0721 , G06F11/073 , G06F11/0793 , G06F12/0875 , G06F12/10 , G06F12/1483 , G06F7/00 , G06F7/483 , G06F9/35 , G06F9/4843 , G06F9/54 , G06F7/49905 , G06F7/4991 , G06F7/49926
摘要： A digital computer system in which data storage is referred to by a descriptor comprising an object number denoting a variable-length block of storage, an offset indicating how far into that block a desired data item begins, and a length field denoting the length of the desired data item. Separate means exist for manipulating each of the three descriptor portions, thus facilitating repetitive operations on related or contiguous operands. Various levels of microcode control are included. Each level of microcode control has its own stack, facilitating interrupts between levels. Stacks are duplicated in "secure stacks" in memory to protect against loss of state data from the stacks.

8. 发明授权

US4499604A Digital data processing system for executing instructions containing operation codes belonging to a plurality of operation code sets and names corresponding to name table entries 失效
标题翻译：数字数据处理系统，用于执行包含属于多个操作码集的操作码和与名称表条目对应的名称的指令
公开(公告)号：US4499604A
公开(公告)日：1985-02-12
申请号：US266423
申请日：1981-05-22
申请人： Gerald F. Clancy , Ronald H. Gruner , Stephen I. Schleimer , Craig J. Mundie , Steven J. Wallach , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein , Richard G. Bratt
发明人： Gerald F. Clancy , Ronald H. Gruner , Stephen I. Schleimer , Craig J. Mundie , Steven J. Wallach , Walter A. Wallach, Jr. , John K. Ahlstrom , Michael S. Richmond , David H. Bernstein , Richard G. Bratt
IPC分类号： G06F9/318 , G06F9/35 , G06F9/30
CPC分类号： G06F9/30192 , G06F9/3017 , G06F9/35
摘要： A digital computer system having a memory for storing and providing data including instructions and a processor for processing data in response to the instructions and providing memory operation specifiers to the memory which specify an address of a data item and the memory operation to be performed on it. The instructions in the digital computer system include operation codes belonging to more than one set of operation codes and names representing items to be processed in the operation specified by the operation code. The data in memory further includes name table entries. Each name table entry corresponds to a name and contains information specifying the address of the item represented by the name. The processor includes apparatus for decoding each operation code in response to the operation code and to a dialect value contained in the decoding apparatus which specifies which operation code set the operation code being decoded belongs to. The processor further includes apparatus for processing names by resolving them to produce the addresses specified by their corresponding name table entries and control apparatus responsive to the instruction decoding apparatus and the name processing apparatus for controlling the processor and providing memory operation specifiers containing the addresses produced by the name processing means to the memory.
摘要翻译：一种数字计算机系统，具有用于存储和提供包括指令的数据的存储器和用于响应于指令处理数据的处理器，并向存储器提供指定数据项的地址的存储器操作说明符以及要对其执行的存储器操作。数字计算机系统中的指令包括属于多于一组操作代码的操作代码和表示在由操作代码指定的操作中要处理的项目的名称。内存中的数据还包括名称表条目。每个名称表项对应一个名称，并包含指定由该名称表示的项目的地址的信息。处理器包括用于响应于操作代码解码每个操作代码的装置和解码装置中包含的指定哪个操作代码设置被解码的操作码属于的方言值的装置。处理器还包括通过解析它们以产生由其对应的名称表格条目和控制装置指定的地址来处理名称的装置，该装置响应于指令解码装置和用于控制处理器的名称处理装置，并提供包含由名称处理意味着记忆。

9. 发明授权

US4445177A Digital data processing system utilizing a unique arithmetic logic unit for handling uniquely identifiable addresses for operands and instructions 失效
公开(公告)号：US4445177A
公开(公告)日：1984-04-24
申请号：US266411
申请日：1981-05-22
申请人： Richard G. Bratt , Stephen I. Schleimer , John F. Pilat , Richard A. Belgard , Steven J. Wallach , Gerald F. Clancy , Craig J. Mundie , David H. Bernstein , Edward S. Gavrin , Thomas M. Jones , Brett L. Bachman
发明人： Richard G. Bratt , Stephen I. Schleimer , John F. Pilat , Richard A. Belgard , Steven J. Wallach , Gerald F. Clancy , Craig J. Mundie , David H. Bernstein , Edward S. Gavrin , Thomas M. Jones , Brett L. Bachman
IPC分类号： G06F9/45 , G06F9/22
CPC分类号： G06F8/41
摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described withreference to the invention herein, indentify locations of object information to be accessed by utilizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format. Arithmetic logic unit (ALU) means, also as particularly described with reference to the invention herein, include general register means having three vertically oriented parts for storing such respective fields. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

10. 发明授权

US4152778A Digital computer memory 失效
标题翻译：数码电脑内存
公开(公告)号：US4152778A
公开(公告)日：1979-05-01
申请号：US728096
申请日：1976-09-30
申请人： Stanley M. Nissen , Steven J. Wallach
发明人： Stanley M. Nissen , Steven J. Wallach
IPC分类号： G06F9/22 , G11C17/00
CPC分类号： G11C17/00 , G06F9/223
摘要： A digital computer memory made up of a plurality of read only memory components arranged in a matrix of rows and columns. The outputs of the columns of memory components are connected to a voltage source and load resistors to provide the output terminals of the memory. Sets of digital words having at least a field or portion of a field with bits represented by the same logical state are grouped in such memory so that, when a word in such set is addressed, the bits in such field are produced at the output terminals by the volage source and load resistors. With such arrangement the number of read only memory components required in such memory is reduced.
摘要翻译：由以列和列的矩阵排列的多个只读存储器组件构成的数字计算机存储器。存储器组件的列的输出连接到电压源和负载电阻器以提供存储器的输出端子。具有至少具有由相同逻辑状态表示的位的字段或场的部分的数字字组被分组在这样的存储器中，使得当这种集合中的字被寻址时，这些字段中的位在输出端产生由电源和负载电阻组成。通过这种布置，这种存储器中所需的只读存储器组件的数量减少了。

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