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1. 发明授权

US6038630A Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses 失效
标题翻译：用于具有多个功能单元的集成系统的共享访问控制设备通过多个数据总线访问外部结构
公开(公告)号：US6038630A
公开(公告)日：2000-03-14
申请号：US47139
申请日：1998-03-24
申请人： Eric M. Foster , Dennis E. Franklin , Stefan P. Jackowski , David Wallach
发明人： Eric M. Foster , Dennis E. Franklin , Stefan P. Jackowski , David Wallach
IPC分类号： G06F13/16 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/1684
摘要： A multi-path access control device for an integrated system is presented which allows simultaneous access to multiple external devices coupled thereto by multiple functional units. The multiple functional units are coupled to the shared access control device across two or more high speed, shared data buses. The control device includes multiple bus ports, each coupled to a different data bus, and a non-blocking crossbar switch coupled to the bus ports for controlling forwarding, with zero cycle latency, of requests from the functional units. Multiple external device ports are coupled to the non-blocking crossbar switch for receiving requests forwarded by the crossbar switch, and each external device is coupled to a different external device port. The crossbar switch allows multiple requests at the bus ports directed to different external devices to be forwarded to different external device ports for simultaneous accessing of different external devices coupled thereto pursuant to the multiple requests.
摘要翻译：提出了一种用于集成系统的多路径访问控制装置，其允许通过多个功能单元同时访问与其耦合的多个外部设备。多个功能单元通过两个或更多个高速共享数据总线耦合到共享访问控制设备。控制设备包括多个总线端口，每个总线端口耦合到不同的数据总线，以及耦合到总线端口的非阻塞交叉开关，用于控制来自功能单元的请求的零周期等待时间的转发。多个外部设备端口耦合到非阻塞交叉开关，用于接收由交叉开关转发的请求，并且每个外部设备耦合到不同的外部设备端口。交叉开关允许在指向不同外部设备的总线端口上的多个请求被转发到不同的外部设备端口，以便根据多个请求同时访问与其耦合的不同外部设备。

2. 发明授权

US5539895A Hierarchical computer cache system 失效
标题翻译：分层计算机缓存系统
公开(公告)号：US5539895A
公开(公告)日：1996-07-23
申请号：US241910
申请日：1994-05-12
申请人： James W. Bishop , Charles E. Carmack, Jr. , Patrick W. Gallagher , Stefan P. Jackowski , Gregory R. Klouda , Robert D. Siegl
发明人： James W. Bishop , Charles E. Carmack, Jr. , Patrick W. Gallagher , Stefan P. Jackowski , Gregory R. Klouda , Robert D. Siegl
IPC分类号： G06F12/08 , G06F12/00 , G06F12/12 , G06F13/00
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0808
摘要： A hierarchical cache system comprises a plurality of first level cache subsystems for storing data or instructions of respective CPUs, a higher level cache subsystem containing data or instructions of the plurality of cache subsystems, and a main memory coupled to the higher level cache subsystem. A page mover is coupled to the higher level cache subsystem and main memory, and responds to a request from one of the CPUs to store data into the main memory, by storing the data into the main memory without copying previous contents of a store-to address of the request to the higher level cache subsystem in response to said request. Also, the page mover invalidates the previous contents in the higher level cache subsystem if already resident there when the CPU made the request. A buffering system within the page mover comprises request buffers and data segment buffers to store a segment of predetermined size of the data. When all of the request buffers have like priority and there are fewer request buffers that contain respective, outstanding requests than the number of data segment buffers, the page mover means allocates to the request buffers with outstanding requests use of the data segment buffers for which there are no outstanding requests.
摘要翻译：分级缓存系统包括用于存储相应CPU的数据或指令的多个第一级高速缓存子系统，包含多个高速缓存子系统的数据或指令的更高级高速缓存子系统以及耦合到较高级缓存子系统的主存储器。页面移动器耦合到较高级缓存子系统和主存储器，并且通过将数据存储到主存储器中来响应来自一个CPU的请求以将数据存储到主存储器中，而不复制存储器的先前内容响应于所述请求向高级缓存子系统发送请求的地址。而且，当CPU发出请求时，页面移动器使上级缓存子系统中的先前内容无效。页面移动器中的缓冲系统包括请求缓冲器和数据段缓冲器，以存储数据的预定大小的段。当所有请求缓冲器都具有优先级，并且存在比数据段缓冲器数量多的请求缓冲器，该请求缓冲器包含与数据段缓冲器数目相对应的未完成请求时，页移动器装置向未请求的请求缓冲器分配请求使用数据段缓冲器没有未完成的请求。

3. 发明申请

US20100132048A1 Protecting Isolated Secret Data of Integrated Circuit Devices 审中-公开
标题翻译：保护集成电路器件的隔离秘密数据
公开(公告)号：US20100132048A1
公开(公告)日：2010-05-27
申请号：US12323670
申请日：2008-11-26
申请人： William E. Hall , Stefan P. Jackowski
发明人： William E. Hall , Stefan P. Jackowski
IPC分类号： G06F21/00
CPC分类号： G06F21/554 , G06F21/78 , G06F21/81 , G06F2221/2143
摘要： A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.
摘要翻译：公开了一种用于控制对设置在集成电路装置的至少一个持续区域的至少一部分中的主秘密数据的访问的电路装置，方法和设计结构。电路装置包括响应于外部时钟信号的时钟电路，被配置为控制集成电路装置的安全状态的安全状态机以及与安全状态机通信并被配置为控制对主机的访问的主秘密电路秘密资料。安全状态机和主秘密电路与时钟电路隔离，并且主秘密电路响应于安全状态机来选择性地擦除主秘密数据的至少一部分。主秘密电路可以被配置为响应于空或触发的安全状态来擦除主秘密数据的部分。

4. 发明授权

US5418909A System for controlling multiple port/multiple channel I/O configuration according to communication request initiation status 失效
标题翻译：根据通信请求启动状态控制多端口/多通道I / O配置的系统
公开(公告)号：US5418909A
公开(公告)日：1995-05-23
申请号：US226221
申请日：1994-04-11
申请人： Stefan P. Jackowski , Ronald B. Jenkins
发明人： Stefan P. Jackowski , Ronald B. Jenkins
IPC分类号： G06F13/14 , G06F13/00 , G06F13/12
CPC分类号： G06F13/126
摘要： The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control indicators are provided for monitoring the communications request initiation status of each channel and each port to achieve expeditious transfers through a selected port between the channel and peripheral devices. The I/O configuration is established responsive to the communications request initiation status that indicates one of several states depending on which side initiates a request and whether the connection has been made.
摘要翻译：计算机系统的I / O配置包括能够在多达四个接口端口上可用的两个信道，其中端口被并入信道内，以便不需要外部交换机。提供控制指示器，用于监视每个通道和每个端口的通信请求启动状态，以实现通道和外围设备之间选定端口的快速传输。响应于通信请求发起状态建立I / O配置，该状态指示根据哪个方启动请求以及是否建立了连接的几种状态之一。

5. 发明授权

US5097410A Multimode data system for transferring control and data information in an I/O subsystem 失效
标题翻译：用于传输I / O子系统中的控制和数据信息的多模数据系统
公开(公告)号：US5097410A
公开(公告)日：1992-03-17
申请号：US292399
申请日：1988-12-30
申请人： Richard L. Hester , Stefan P. Jackowski , Peter N. James , James T. Moyer , Robert G. Rush , Gregory S. Ulsh , Mark J. Wolski
发明人： Richard L. Hester , Stefan P. Jackowski , Peter N. James , James T. Moyer , Robert G. Rush , Gregory S. Ulsh , Mark J. Wolski
IPC分类号： G06F13/12
CPC分类号： G06F13/122
摘要： A system structured to transfer control information between an IFA (I/O interface adapter) and an I/O processor, and I/O data between an IFA and a CDB (channel data buffer) has separate interfaces for these transfers. The control interface includes a multi-mode, bidirectional control data bus, a control mode bus for establishing the mode of the bus, and a check interface on which the IFA provides error information. The data interface includes a multi-mode, bidirectional data transfer bus, respective SYNC and ACCEPT lines for transferring time-phased control signals to establish the mode of the data transfer bus, and a parity line to indicate to the IFA the parity of the SYNC and ACCEPT lines.

6. 发明授权

US06968415B2 Opaque memory region for I/O adapter transparent bridge 有权
标题翻译：不透明内存区域用于I / O适配器透明桥
公开(公告)号：US06968415B2
公开(公告)日：2005-11-22
申请号：US10113299
申请日：2002-03-29
申请人： Timothy C. Bronson , Stefan P. Jackowski , John M. Sheplock , Phillip G. Williams
发明人： Timothy C. Bronson , Stefan P. Jackowski , John M. Sheplock , Phillip G. Williams
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4059
摘要： An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.
摘要翻译：用于I / O适配器的桥的不透明的存储器区域。不透明的存储器区域无法通过从主总线到次总线或辅助总线到主总线的桥接器的存储器事务。因此，桥接器忽略了针对不透明存储器区域的内存事务，允许在每个存储不同数据的网桥两侧存在相同的地址。不透明存储器区域的实现提供了在I / O适配器子系统存储器内完成存储器事务的手段，因此减轻了主机计算机系统存储器资源。此外，主机和所有I / O设备使用一些相同的内存地址的主机系统中可以使用多个I / O适配器。

7. 发明授权

US4809273A Device for verifying operation of a checking code generator 失效
标题翻译：用于验证检查码发生器的操作的装置
公开(公告)号：US4809273A
公开(公告)日：1989-02-28
申请号：US8505
申请日：1987-01-29
申请人： Stefan P. Jackowski , Ronald B. Jenkins
发明人： Stefan P. Jackowski , Ronald B. Jenkins
IPC分类号： G06F11/10 , G06F11/267 , H03M13/00 , G06F11/12
CPC分类号： G06F11/2215 , G06F11/10
摘要： A system for ensuring accurate transmission of data between two functional units. A checking code generator is provided and a device operatively connected to the checking code generator ensures proper operation thereof.

8. 发明授权

US10452844B2 Protecting isolated secret data of integrated circuit devices 有权
公开(公告)号：US10452844B2
公开(公告)日：2019-10-22
申请号：US12323670
申请日：2008-11-26
申请人： William E. Hall , Stefan P. Jackowski
发明人： William E. Hall , Stefan P. Jackowski
IPC分类号： G06F21/55 , G06F21/78 , G06F21/81
摘要： A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.

9. 发明授权

US5539875A Error windowing for storage subsystem recovery 失效
标题翻译：存储子系统恢复错误窗口
公开(公告)号：US5539875A
公开(公告)日：1996-07-23
申请号：US367389
申请日：1994-12-30
申请人： James W. Bishop , Mark L. Ciacelli , Patrick W. Gallagher , Stefan P. Jackowski , Gregory R. Klouda , Robert D. Siegl
发明人： James W. Bishop , Mark L. Ciacelli , Patrick W. Gallagher , Stefan P. Jackowski , Gregory R. Klouda , Robert D. Siegl
IPC分类号： G06F11/14 , G01R31/28 , G06F11/00
CPC分类号： G06F11/1435
摘要： In a hierarchical, multi-level storage system, recovery from intermittent storage hardware failures is supported by establishing hardware checkpoints at storage system interfaces and by duplication of subsystem hardware within units of the storage system. When error is detected at an interface, all levels of the storage system are quiesced and backed up to a point preceding the occurrence of the error. If a hardware failure causes an error, the system is quiesced while the failed hardware is reconfigured with control logic copied from duplicate hardware. A single restart command restarts system operation.
摘要翻译：在分层的多级存储系统中，通过在存储系统接口上建立硬件检查点，并通过在存储系统的单元内复制子系统硬件来支持间歇性存储硬件故障的恢复。当在接口检测到错误时，存储系统的所有级别都将被停顿并备份到错误发生之前。如果硬件故障导致错误，则系统将在从重复的硬件复制的控制逻辑重新配置故障硬件时停顿。单个重新启动命令重新启动系统操作。

10. 发明授权

US5303351A Error recovery in a multiple 170 channel computer system 失效
标题翻译：多个I / O通道计算机系统中的错误恢复
公开(公告)号：US5303351A
公开(公告)日：1994-04-12
申请号：US856832
申请日：1992-03-23
申请人： Stefan P. Jackowski , Ronald B. Jenkins
发明人： Stefan P. Jackowski , Ronald B. Jenkins
IPC分类号： G06F13/12 , G06F13/14
CPC分类号： G06F13/126
摘要： The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control means are provided for monitoring the status of each channel and each port in order to achieve expeditious transfers through a selected port between the channel and peripheral devices. Error reporting is limited to the area directly affected by the error, and immediate disconnection helps to isolate the error and allow time for error recovery before the particular channel or port again becomes available.
摘要翻译：计算机系统的I / O配置包括能够在多达四个接口端口上可用的两个信道，其中端口被并入信道内，以便不需要外部交换机。提供控制装置用于监视每个通道和每个端口的状态，以便通过通道和外围设备之间的选定端口实现快速传输。错误报告仅限于由错误直接影响的区域，立即断开有助于隔离错误，并允许在特定通道或端口再次可用之前进行错误恢复的时间。

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