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    • 10. 发明授权
    • Iterative decoder and an iterative decoding method for a communication system
    • 迭代解码器和通信系统的迭代解码方法
    • US06615385B1
    • 2003-09-02
    • US09475684
    • 1999-12-30
    • Min-Goo KimBeong-Jo KimYoung-Hwan LeeSoon-Jae Choi
    • Min-Goo KimBeong-Jo KimYoung-Hwan LeeSoon-Jae Choi
    • H03M1329
    • H03M13/2975H03M13/09H03M13/27
    • An iterative decoder and iterative decoding method. In the iterative decoder, a first adder has a first port for receiving information symbols and a second port. A first component decoder which is coupled to the first adder, receives first parity symbols and decodes the information symbols using first parity symbols and an output signal of the first adder. A first subtractor has a third port for receiving the output of the first component decoder, and a fourth port. An interleaver which is coupled to the output of the first subtractor, interleaves the decoded information symbols received from the first component decoder. A second component decoder receives the output of the interleaver and second parity symbols and decodes the information symbols of the interleaver output using the received signals. A deinterleaver deinterleaves the output of the second component decoder. A second subtractor has a fifth port for receiving the output of the deinterleaver and a sixth port for receiving an inverted output of the first subtractor. The output of the second subtractor is connected to the second port and an inverted output of the second subtractor is connected to the fourth port. A hard decision device converts the decoded symbols received from the first component decoder to binary information bits. An error detector checks errors in the binary information bits received from the hard decision device and generates a no error signal if no errors are detected. An output buffer stores the binary information bits received from the hard decision device and outputs the stored binary information bits in response to the no error signal.
    • 迭代解码和迭代解码方法。 在迭代解码器中,第一加法器具有用于接收信息符号的第一端口和第二端口。 耦合到第一加法器的第一分量解码器接收第一奇偶校验符号并使用第一奇偶校验符号和第一加法器的输出信号对信息符号进行解码。 第一减法器具有用于接收第一分量解码器的输出的第三端口和第四端口。 耦合到第一减法器的输出的交织器交错从第一分量解码器接收的解码信息符号。 第二分量解码器接收交织器的输出和第二奇偶校验符号,并使用接收的信号对交织器输出的信息符号进行解码。 解交织器解交织第二分量解码器的输出。 第二减法器具有用于接收解交织器的输出的第五端口和用于接收第一减法器的反相输出的第六端口。 第二减法器的输出连接到第二端口,第二减法器的反相输出端连接到第四端口。 硬判决装置将从第一分量解码器接收的解码符号转换为二进制信息比特。 错误检测器检查从硬判决装置接收的二进制信息比特中的错误,并且如果没有检测到错误则产生无错误信号。 输出缓冲器存储从硬判决装置接收到的二进制信息比特,并响应于无错误信号输出存储的二进制信息比特。