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1. 发明授权

US08785272B2 Process to make high-K transistor dielectrics 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US08785272B2
公开(公告)日：2014-07-22
申请号：US13224059
申请日：2011-09-01
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/00 , H01L21/28 , H01L21/314
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

2. 发明申请

US20130324196A1 CONTROL OF ACTIVATION OF LOCATION-RELATED SENSORS OF A MOBILE DEVICE 有权
标题翻译：控制移动设备的位置相关传感器的激活
公开(公告)号：US20130324196A1
公开(公告)日：2013-12-05
申请号：US13907863
申请日：2013-06-01
申请人： Chenyu Wang , Jun Yang , Sam Song Liang
发明人： Chenyu Wang , Jun Yang , Sam Song Liang
IPC分类号： H04W52/02
CPC分类号： H04W52/0254 , G01S19/34 , G06F1/00 , G06F1/3215 , G06F1/325 , G06F9/00 , H04M1/72572 , H04M2250/12 , H04W4/02 , H04W52/283 , Y02D70/142 , Y02D70/164
摘要： Methods, systems and apparatuses for selecting which of a plurality of sensors to use for location detection of a mobile device are disclosed. One method includes activating lowest-power location-related sensors of the mobile device at power up of a mobile device, and activating medium-power location-related sensors of the mobile device upon detection of motion of the mobile device and/or a change in a wireless connection to the mobile device.
摘要翻译：公开了用于选择用于移动设备的位置检测的多个传感器中的哪一个的方法，系统和装置。一种方法包括在移动设备上电时激活移动设备的最低功率位置相关传感器，以及在检测到移动设备的运动时激活移动设备的中功率位置相关传感器和/或与移动设备的无线连接。

3. 发明授权

US08552522B2 Dishing-free gap-filling with multiple CMPs 有权
公开(公告)号：US08552522B2
公开(公告)日：2013-10-08
申请号：US13151666
申请日：2011-06-02
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/70
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

4. 发明授权

US08461629B2 Semiconductor device and method of fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08461629B2
公开(公告)日：2013-06-11
申请号：US13178755
申请日：2011-07-08
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

5. 发明授权

US08125051B2 Device layout for gate last process 有权
标题翻译：门最后进程的设备布局
公开(公告)号：US08125051B2
公开(公告)日：2012-02-28
申请号：US12471091
申请日：2009-05-22
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
IPC分类号： H01L27/06 , H01L21/70 , H01L21/338 , H01L21/302
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要： A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

6. 发明申请

US20120025329A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20120025329A1
公开(公告)日：2012-02-02
申请号：US13270585
申请日：2011-10-11
申请人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/78
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

7. 发明授权

US07998830B2 Semiconductor device with both I/O and core components and method of fabricating same 有权
标题翻译：具有I / O和核心部件的半导体器件及其制造方法
公开(公告)号：US07998830B2
公开(公告)日：2011-08-16
申请号：US12961167
申请日：2010-12-06
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

8. 发明申请

US20110195608A1 ELECTRICAL CONNECTOR WITH IMPROVED RECEIVING CHANNELS LATCHED WITH CONTACTS 失效
标题翻译：具有改进的接收通道的电气连接器
公开(公告)号：US20110195608A1
公开(公告)日：2011-08-11
申请号：US13015289
申请日：2011-01-27
申请人： YUN-SONG SUN , SONG-LIANG WANG , CHIEN-HSUN HUANG
发明人： YUN-SONG SUN , SONG-LIANG WANG , CHIEN-HSUN HUANG
IPC分类号： H01R24/00
CPC分类号： H01R13/40 , H01R9/03
摘要： An electrical connector (100), comprising an insulative housing (1) and a plurality of contacts (2) received in the insulative housing. The insulative housing defines a base portion (11) and a mating portion (12) in front of the base portion, the mating portion defines a plurality of receiving channels (124) extending along a mating direction. The contacts are received in the insulative housing, and inserted into the receiving channels along a front-to-back direction. Each contact has a soldering portion (21) extending through the receiving channel and assembled to the base portion of the insulative housing, a retaining portion (23) located in front of the soldering portion and held in the receiving channel, and a contacting portion (24) received in the mating portion of the insulative housing, the retaining portion has a higher barb (231) in the front and a lower barb (232) on a rear section thereof on both sides.
摘要翻译：一种电连接器（100），包括绝缘壳体（1）和容纳在绝缘壳体中的多个触点（2）。绝缘壳体在基部前面限定了基部部分（11）和配合部分（12），所述配合部分限定沿着配合方向延伸的多个接纳通道（124）。触点被接收在绝缘壳体中，并且沿着前后方向插入接收通道。每个触点具有延伸穿过接收通道并组装到绝缘壳体的基部的焊接部分（21），位于焊接部分前面并保持在接收通道中的保持部分（23）和接触部分 24）接收在绝缘壳体的配合部分中，保持部分在前侧具有较高的倒钩（231）和在其两侧的后部上的下倒钩（232）。

9. 发明授权

US07898037B2 Contact scheme for MOSFETs 有权
标题翻译： MOSFET的接触方案
公开(公告)号：US07898037B2
公开(公告)日：2011-03-01
申请号：US11833128
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Jung-Hui Kao , Sheng-Chen Chung , Chung Long Cheng , Shun-Jang Liao
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Jung-Hui Kao , Sheng-Chen Chung , Chung Long Cheng , Shun-Jang Liao
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。

10. 发明授权

US07868361B2 Semiconductor device with both I/O and core components and method of fabricating same 有权
公开(公告)号：US07868361B2
公开(公告)日：2011-01-11
申请号：US11766425
申请日：2007-06-21
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

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