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1. 发明授权

US08988958B2 Sense amplifier circuit and semiconductor device 有权
公开(公告)号：US08988958B2
公开(公告)日：2015-03-24
申请号：US14306293
申请日：2014-06-17
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C5/14 , G11C7/10
CPC分类号： G11C7/06 , G11C5/147 , G11C7/065 , G11C7/067 , G11C7/1087 , G11C11/4091
摘要： A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

2. 发明申请

US20100054066A1 Memory device, semiconductor memory device and control method thereof 有权
标题翻译：存储器件，半导体存储器件及其控制方法
公开(公告)号：US20100054066A1
公开(公告)日：2010-03-04
申请号：US12461770
申请日：2009-08-24
申请人： Kazuhiko Kajigaya , Soichiro Yoshida
发明人： Kazuhiko Kajigaya , Soichiro Yoshida
IPC分类号： G11C7/02 , G11C7/00 , G11C8/08
CPC分类号： G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.
摘要翻译：半导体存储器件包括存储单元阵列，第一和第二位线，第一和第二放大器以及读出放大器控制电路。第一读出放大器中的放大元件放大第一位线的信号并将其转换为输出电流。第二位线经由第一读出放大器选择性地连接到第一位线。第二读出放大器中的信号电压判定单元确定被提供有输出电流的第二位线的信号电平。读出放大器控制电路根据在正常操作中的第一定时将上述连接从连接状态切换到断开状态的确定定时来控制放大元件与单元之间的连接，并以相同的方式在一个在刷新操作中延迟第二定时。

3. 发明申请

US20090257298A1 Semiconductor device having single-ended sensing amplifier 有权
标题翻译：具有单端感测放大器的半导体器件
公开(公告)号：US20090257298A1
公开(公告)日：2009-10-15
申请号：US12382494
申请日：2009-03-17
申请人： Kazuhiko Kajigaya , Soichiro Yoshida
发明人： Kazuhiko Kajigaya , Soichiro Yoshida
IPC分类号： G11C7/02 , G11C7/00 , G11C11/22
CPC分类号： G11C8/08 , G11C7/067 , G11C11/22 , G11C11/223 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004
摘要： A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit line, and a global bit line voltage determination circuit; and at least the ON/OFF timing of the second MOS transistor or the read timing of a global sense amplifier that includes the global bit line voltage determination circuit is controlled by the output signal of a delay circuit that includes a replica of the first MOS transistor and a replica of the global bit line voltage determination circuit.
摘要翻译：具有分层位线结构的半导体存储装置中的单端读出放大器包括：第一MOS晶体管，用于将从存储单元输出的信号放大到位线;第二MOS晶体管，用于将第一MOS晶体管的输出馈送到全局位线和全局位线电压确定电路; 并且包括全局位线电压确定电路的至少第二MOS晶体管的ON / OFF定时或包括全局位线电压确定电路的全局读出放大器的读取定时由包括第一MOS晶体管的复制品的延迟电路的输出信号控制以及全局位线电压确定电路的副本。

4. 发明申请

US20090251948A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090251948A1
公开(公告)日：2009-10-08
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24 , G11C7/06 , G11C7/00
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译：在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过对存储器单元适当地执行重新加载操作全局局部感测放大器。因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

5. 发明申请

US20080093931A1 POWER SUPPLY VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：电源电压发生电路和半导体集成电路设备
公开(公告)号：US20080093931A1
公开(公告)日：2008-04-24
申请号：US11875235
申请日：2007-10-19
申请人： Soichiro YOSHIDA
发明人： Soichiro YOSHIDA
IPC分类号： H02J1/00
CPC分类号： H02J7/0065 , G05F1/465 , Y10T307/696
摘要： Required minimum power supply voltage for a load circuit is maintained. Power supply voltage generating circuit 10 comprises a power supply circuit 11 that steps down a voltage of an external power supply VCC based on a reference voltage VREF and supplies it to a power supply VINT of a load circuit 14, and a power supply circuit 12 that steps down a voltage of a step-up voltage power supply VPP based on a reference voltage VREF-ΔV, which is closer to the ground potential than the reference voltage VREF, and supplies it to the power supply VINT of the load circuit 14. The power supply circuit 12 supplies power to the power supply VINT of the load circuit 14 when the voltage of the power supply VINT is below the reference voltage VREF-ΔV. Further, a voltage step-up power supply circuit 13 generates a step-up power supply voltage VPP, which is a voltage higher than the voltage of the external power supply VCC, and supplies it to the power supply circuit 12. The load circuit 14 is comprised of various circuits operated by the power supply VINT.
摘要翻译：维持负载电路所需的最小电源电压。电源电压发生电路10包括：电源电路11，其根据参考电压VREF降压外部电源VCC的电压，并将其提供给负载电路14的电源VINT;以及电源电路12，基于比参考电压VREF更接近地电位的参考电压VREF-DeltaV来降压升压电压电源VPP的电压，并将其提供给负载电路14的电源VINT。当电源VINT的电压低于参考电压VREF-DeltaV时，电源电路12向负载电路14的电源VINT供电。此外，升压电源电路13生成比外部电源VCC的电压高的升压电源电压VPP，并将其提供给电源电路12。负载电路14包括由电源VINT操作的各种电路。

6. 发明授权

US08872258B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08872258B2
公开(公告)日：2014-10-28
申请号：US13359453
申请日：2012-01-26
申请人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
发明人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
IPC分类号： H01L29/66
CPC分类号： H01L27/10897 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , H01L21/823487 , H01L27/0207
摘要： A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.
摘要翻译：半导体存储器件包括：读出放大器; 多个存储单元阵列; 共享MOS晶体管，其连接/断开读出放大器和存储单元阵列中包含的位线; 以及控制所述共享MOS晶体管的动作的控制电路。作为连接读出放大器和共享MOS晶体管的位线的读出放大器位线的一部分或全部嵌入在半导体衬底中。

7. 发明申请

US20140293721A1 SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE 有权
标题翻译： SENSE放大器电路和半导体器件
公开(公告)号：US20140293721A1
公开(公告)日：2014-10-02
申请号：US14306293
申请日：2014-06-17
申请人： Kazuhiko KAJIGAYA , Soichiro YOSHIDA , Yasutoshi YAMADA
发明人： Kazuhiko KAJIGAYA , Soichiro YOSHIDA , Yasutoshi YAMADA
IPC分类号： G11C11/4091
CPC分类号： G11C7/06 , G11C5/147 , G11C7/065 , G11C7/067 , G11C7/1087 , G11C11/4091
摘要： A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.
摘要翻译：本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。

8. 发明授权

US08576610B2 Semiconductor device having floating body type transistor 失效
标题翻译：具有浮体型晶体管的半导体器件
公开(公告)号：US08576610B2
公开(公告)日：2013-11-05
申请号：US13184072
申请日：2011-07-15
申请人： Soichiro Yoshida
发明人： Soichiro Yoshida
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C7/067 , G11C7/1069 , G11C11/4096 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： A semiconductor device is disclosed in which a signal line and a drive circuit driving the signal line in response to a signal to be transmitted are provided. A transistor of a floating body type is further provided that includes a gate, a source, a drain, and a body between the source and drain which is brought into an electrically floating state. The gate is connected to the signal line, and at least one of the source and drain is connected to a control node that is supplied with a control signal. The control signal is configured to receive a control signal that changes from the first level to a second level during the period of time when the drive circuit is driving the signal node.
摘要翻译：公开了一种半导体器件，其中提供了响应于要发送的信号驱动信号线的信号线和驱动电路。还提供一种浮体晶体管，其包括位于源极和漏极之间的栅极，源极，漏极和主体，其被带入电浮动状态。栅极连接到信号线，源极和漏极中的至少一个连接到被提供控制信号的控制节点。控制信号被配置为在驱动电路驱动信号节点的时段期间接收从第一电平变化到第二电平的控制信号。

9. 发明申请

US20130193507A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130193507A1
公开(公告)日：2013-08-01
申请号：US13359453
申请日：2012-01-26
申请人： Soichiro YOSHIDA , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
发明人： Soichiro YOSHIDA , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
IPC分类号： H01L27/088
CPC分类号： H01L27/10897 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , H01L21/823487 , H01L27/0207
摘要： A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.

10. 发明授权

US08189413B2 Semiconductor memory device, test method thereof and semiconductor device 失效
标题翻译：半导体存储器件，其测试方法和半导体器件
公开(公告)号：US08189413B2
公开(公告)日：2012-05-29
申请号：US12549184
申请日：2009-08-27
申请人： Soichiro Yoshida
发明人： Soichiro Yoshida
IPC分类号： G11C29/00 , G11C7/02 , G11C7/00
CPC分类号： G11C29/02 , G11C11/4091 , G11C11/4097 , G11C29/026 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor memory device comprises a memory cell array having memory cells including a plurality of memory cells, and also comprises a first bit line, a first sense amplifier circuit and a control circuit. A signal is read out from a selected memory cell of the memory cell array through the first bit line. The first sense amplifier circuit has a single-ended configuration and includes an amplifying element amplifying a signal voltage of the first bit line so as to convert the signal voltage into an output current. The control circuit controls a test operation to measure a current flowing in the first sense amplifier circuit independently of currents flowing in other circuit portions.
摘要翻译：半导体存储器件包括存储单元阵列，其具有包括多个存储单元的存储单元，并且还包括第一位线，第一读出放大器电路和控制电路。通过第一位线从存储单元阵列的选定存储单元中读出信号。第一读出放大器电路具有单端配置，并且包括放大元件，放大第一位线的信号电压，以将信号电压转换为输出电流。控制电路控制测试操作以独立于在其它电路部分中流动的电流来测量在第一读出放大器电路中流动的电流。

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