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1. 发明申请

US20110157990A1 CONTROL DEVICE FOR NONVOLATILE MEMORY AND METHOD OF OPERATING CONTROL DEVICE 有权
标题翻译：非易失性存储器的控制装置和操作控制装置的方法
公开(公告)号：US20110157990A1
公开(公告)日：2011-06-30
申请号：US12914131
申请日：2010-10-28
申请人： Shunichi TOYAMA
发明人： Shunichi TOYAMA
IPC分类号： G11C16/10 , G11C16/34 , G11C16/12 , G11C16/04 , G11C16/26
CPC分类号： G11C16/32 , G11C16/04 , G11C16/10 , G11C16/3418
摘要： A device comprises a nonvolatile memory cell array, a buffer circuit, a program control circuit, and a read control circuit. The nonvolatile memory cell array comprises a plurality of memory cells. The program control circuit stores program data in the buffer circuit. The read control circuit reads data from a selected address of the nonvolatile memory cell array. The program control circuit compares the program data with the read data, and sets a bit of the program data as a program-inhibit bit based on the comparison.
摘要翻译：一种设备包括非易失性存储单元阵列，缓冲电路，程序控制电路和读控制电路。非易失性存储单元阵列包括多个存储单元。程序控制电路将程序数据存储在缓冲电路中。读取控制电路从非易失性存储单元阵列的选定地址读取数据。程序控制电路将程序数据与读取的数据进行比较，并且基于比较将程序数据的位设置为程序禁止位。

2. 发明申请

US20080123428A1 Semiconductor memory device and method of verifying the same 失效
标题翻译：半导体存储器件及其验证方法
公开(公告)号：US20080123428A1
公开(公告)日：2008-05-29
申请号：US11819173
申请日：2007-06-26
申请人： Makoto Senoo , Kazunari Kido , Shunichi Toyama , Yoshihiro Tsukidate
发明人： Makoto Senoo , Kazunari Kido , Shunichi Toyama , Yoshihiro Tsukidate
IPC分类号： G11C7/22
CPC分类号： G11C16/3454 , G11C2216/20
摘要： Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.
摘要翻译：示例性实施例提供半导体存储器件及其验证方法。半导体存储器件可以包括：包括多个存储器单元的存储器; 确定存储器中的存储器单元的程序状态的验证器; 和/或控制存储器和验证器的地址/程序控制器。示例实施例包括在存储器单元的操作期间使存储器开始暂停操作，和/或当挂起操作终止时开始验证操作。如果确定需要重复操作，则地址/程序控制器可以在存储器单元上开始操作，并且如果确定不需要重复操作，则可以在下一个存储器单元上开始编程操作。存储器操作模式可以是在编程之前不执行验证操作的模式。

3. 发明授权

US08446768B2 Control device for nonvolatile memory and method of operating control device 有权
标题翻译：非易失性存储器的控制装置和操作控制装置的方法
公开(公告)号：US08446768B2
公开(公告)日：2013-05-21
申请号：US12914131
申请日：2010-10-28
申请人： Shunichi Toyama
发明人： Shunichi Toyama
IPC分类号： G11C16/04
CPC分类号： G11C16/32 , G11C16/04 , G11C16/10 , G11C16/3418
摘要： A device comprises a nonvolatile memory cell array, a buffer circuit, a program control circuit, and a read control circuit. The nonvolatile memory cell array comprises a plurality of memory cells. The program control circuit stores program data in the buffer circuit. The read control circuit reads data from a selected address of the nonvolatile memory cell array. The program control circuit compares the program data with the read data, and sets a bit of the program data as a program-inhibit bit based on the comparison.
摘要翻译：一种设备包括非易失性存储单元阵列，缓冲电路，程序控制电路和读控制电路。非易失性存储单元阵列包括多个存储单元。程序控制电路将程序数据存储在缓冲电路中。读取控制电路从非易失性存储单元阵列的选定地址读取数据。程序控制电路将程序数据与读取的数据进行比较，并且基于比较将程序数据的位设置为程序禁止位。

4. 发明授权

US08094495B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08094495B2
公开(公告)日：2012-01-10
申请号：US12615472
申请日：2009-11-10
申请人： Shunichi Toyama
发明人： Shunichi Toyama
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C2211/5646
摘要： A nonvolatile memory device includes a data memory cell array having multi level memory cells divided into two groups, a write sequence memory cell array configured to store a write sequence indicating in which of the two groups the multi level data was written first, and a write time memory cell array configured to store the number of write operations performed on the memory cells. The memory device further includes a control circuit configured to control a program operation by determining allocation of data corresponding to a minimum physical voltage distribution causing a reaction of the memory cells, such that a shift of a first minimum physical voltage causing a reaction due to the first write operation and a shift of a second minimum physical voltage causing a reaction due to the second write operation are equal regardless of write sequence.
摘要翻译：非易失性存储器件包括具有被分成两组的多级存储器单元的数据存储单元阵列，写入序列存储单元阵列被配置为存储指示在两组中的哪一个中首先写入多级数据的写入序列，以及写入配置为存储对存储器单元执行的写入操作的次数的时间存储单元阵列。存储装置还包括控制电路，其被配置为通过确定对应于导致存储器单元的反应的最小物理电压分布的数据的分配来控制编程操作，使得由于第一最小物理电压而导致由于第一写入操作和由于第二写入操作引起的反应的第二最小物理电压的移位与写入顺序无关。

5. 发明申请

US20100128527A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20100128527A1
公开(公告)日：2010-05-27
申请号：US12615472
申请日：2009-11-10
申请人： Shunichi Toyama
发明人： Shunichi Toyama
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C2211/5646
摘要： A nonvolatile memory device includes a data memory cell array having multi level memory cells divided into two groups, a write sequence memory cell array configured to store a write sequence indicating in which of the two groups the multi level data was written first, and a write time memory cell array configured to store the number of write operations performed on the memory cells. The memory device further includes a control circuit configured to control a program operation by determining allocation of data corresponding to a minimum physical voltage distribution causing a reaction of the memory cells, such that a shift of a first minimum physical voltage causing a reaction due to the first write operation and a shift of a second minimum physical voltage causing a reaction due to the second write operation are equal regardless of write sequence.
摘要翻译：非易失性存储器件包括具有被分成两组的多级存储器单元的数据存储单元阵列，写入序列存储单元阵列被配置为存储指示在两组中的哪一个中首先写入多级数据的写入序列，以及写入配置为存储对存储器单元执行的写入操作的次数的时间存储单元阵列。存储装置还包括控制电路，其被配置为通过确定对应于导致存储器单元的反应的最小物理电压分布的数据的分配来控制编程操作，使得由于第一最小物理电压而导致由于第一写入操作和由于第二写入操作引起的反应的第二最小物理电压的移位与写入顺序无关。

6. 发明授权

US07593266B2 Semiconductor memory device and method of verifying the same 失效
标题翻译：半导体存储器件及其验证方法
公开(公告)号：US07593266B2
公开(公告)日：2009-09-22
申请号：US11819173
申请日：2007-06-26
申请人： Makoto Senoo , Kazunari Kido , Shunichi Toyama , Yoshihiro Tsukidate
发明人： Makoto Senoo , Kazunari Kido , Shunichi Toyama , Yoshihiro Tsukidate
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C2216/20
摘要： Example embodiments provide a semiconductor memory device and a method of verifying the same. The semiconductor memory device may include: a memory including a plurality of memory cells; a verifier determining a program state of the memory cell in the memory; and/or an address/program controller controlling the memory and the verifier. Example embodiments include making the memory start a suspend operation during an operation of the memory cell, and/or starting a verify operation when the suspend operation terminates. The address/program controller may start the operation on the memory cell if it is determined that a repeat operation is necessary, and may start the program operation on the next memory cell if it is determined that a repeat operation is unnecessary. The memory operation mode may be one in which a verify operation is not performed before programming.
摘要翻译：示例性实施例提供半导体存储器件及其验证方法。半导体存储器件可以包括：包括多个存储器单元的存储器; 确定存储器中的存储器单元的程序状态的验证器; 和/或控制存储器和验证器的地址/程序控制器。示例实施例包括在存储器单元的操作期间使存储器开始暂停操作，和/或当挂起操作终止时开始验证操作。如果确定需要重复操作，则地址/程序控制器可以在存储器单元上开始操作，并且如果确定不需要重复操作，则可以在下一个存储器单元上开始编程操作。存储器操作模式可以是在编程之前不执行验证操作的模式。

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