会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    • 半导体器件及其制造方法
    • US20110233607A1
    • 2011-09-29
    • US13050818
    • 2011-03-17
    • Satoshi YanagisawaShuji Kamata
    • Satoshi YanagisawaShuji Kamata
    • H01L29/739H01L21/331
    • H01L29/7397H01L29/0623H01L29/0653H01L29/0834H01L29/4236
    • According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a control electrode. The first semiconductor region is provided selectively on a first major surface of the first semiconductor layer. The second semiconductor region is provided selectively on the first major surface in contact with the first semiconductor region. The third semiconductor region is provided selectively on a surface of the first semiconductor region. The fourth semiconductor region is provided to face a projecting surface between a side surface and a bottom surface of the first semiconductor region with the second semiconductor region interposed. The control electrode is provided on the first semiconductor layer, the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film.
    • 根据一个实施例,半导体器件包括第一导电类型的第一半导体层,第二导电类型的第一半导体区域,第一导电类型的第二半导体区域,第一导电类型的第三半导体区域, 第二导电类型的第四半导体区域和控制电极。 第一半导体区域选择性地设置在第一半导体层的第一主表面上。 选择性地在与第一半导体区域接触的第一主表面上提供第二半导体区域。 第三半导体区域选择性地设置在第一半导体区域的表面上。 第四半导体区域被设置为面对第一半导体区域的侧表面和底表面之间的突出表面,并且第二半导体区域被插入。 控制电极经由绝缘膜设置在第一半导体层,第一半导体区域,第二半导体区域和第三半导体区域上。
    • 4. 发明申请
    • POWER SEMICONDUCTOR DEVICE
    • 功率半导体器件
    • US20120241814A1
    • 2012-09-27
    • US13425250
    • 2012-03-20
    • Shuji KAMATAMasakazu Kobayashi
    • Shuji KAMATAMasakazu Kobayashi
    • H01L29/739
    • H01L29/7397H01L29/0834H01L29/51
    • A power semiconductor device includes a p-type collector layer, an n-type base layer, a p-type base layer, an n-type source layer, and a gate electrode. The gate electrode is formed in a trench running from a surface of the n-type source layer through the n-type source layer and the p-type base layer to an interior of the n-type base layer via a gate insulating film. The gate electrode includes a first portion and a second portion. The first portion is opposed to a bottom end portion of the p-type base layer. The second portion is opposed to an upper end portion of the p-type base layer. The gate electrode is formed such that a threshold at the bottom end portion of the p-type base layer is not less than a threshold at the upper end portion of the p-type base layer.
    • 功率半导体器件包括p型集电极层,n型基极层,p型基极层,n型源极层和栅电极。 栅电极形成在从n型源极的表面通过n型源极层和p型基极层经由栅极绝缘膜向n型基极层的内部延伸的沟槽中。 栅电极包括第一部分和第二部分。 第一部分与p型基底层的底端部分相对。 第二部分与p型基底层的上端部相对。 栅电极形成为使p型基极层的底端部的阈值为p型基底层的上端部的阈值以上。