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1. 发明申请

US20080283872A1 Variable path wiring cell, semiconductor integrated circuit designing method thereof, and forming method of variable path wiring cell 审中-公开
标题翻译：可变路径布线单元，半导体集成电路设计方法和可变路径布线单元的形成方法
公开(公告)号：US20080283872A1
公开(公告)日：2008-11-20
申请号：US11898696
申请日：2007-09-14
申请人： Junji Kubo , Atsushi Yamamoto , Shoji Takaoka
发明人： Junji Kubo , Atsushi Yamamoto , Shoji Takaoka
IPC分类号： H01L23/525 , G06F17/50 , H01L21/4763
CPC分类号： H01L27/0203 , H01L27/11803
摘要： Provided are a first wiring layer where each of the first, second internally present wirings can be selectively connected to the first and the second externally extended wirings, and a second wiring layer that has substantially the same structure as that of the first wiring layer. There is further provided an interlayer contact layer which arbitrarily connects one of the first and the second internally present wirings on the first wiring layer to one of the first, second internally present wirings on the second wiring layer, and connects the remainder of the first and the second internally present wirings on the first wiring layer to the remainder of the first and the second internally present wirings on the second wiring layer.
摘要翻译：提供了第一布线层，其中第一，第二内部布线中的每一个可以选择性地连接到第一和第二外部延伸的布线，以及具有与第一布线层基本相同的结构的第二布线层。还提供了层间接触层，其将第一布线层上的第一和第二内部布线中的一个任意地连接到第二布线层上的第一，第二内部布线中的一个，并将第一和第二布线层的剩余部分在第一布线层上的第二内部存在布线到第二布线层上的第一和第二内部布线的其余部分。

2. 发明授权

US5687922A Pulverizer 失效
标题翻译：粉碎机
公开(公告)号：US5687922A
公开(公告)日：1997-11-18
申请号：US539927
申请日：1995-10-06
申请人： Shoji Takaoka
发明人： Shoji Takaoka
IPC分类号： A47J42/06 , B02C2/10 , B02C19/08
CPC分类号： B02C2/10 , A47J42/06
摘要： A pulverizer used to pulverize tea leaves, grain such as sesame and wheat, and minerals such as ceramics and rocks. A pair of upper and lower mortars provided for the pulverizer are rotated relatively to pulverize material between the pulverizing surface provided on the top surface of the lower mortar and the pulverizing surface provided on the bottom surface of the upper mortar. The pulverizing surface of the lower mortar is formed in a concave conical shape and the pulverizing surface of the upper mortar is formed in a conical shape matching the concave conical shape. Accordingly, when pulverization is performed between the pulverizing surfaces of the upper and lower mortars, the material is raised along the pulverizing surface of the lower mortar toward its outer peripheral section and slips down along the pulverizing surface, returning toward its central section. This up-and-down movement is repeated. The material can therefore be retained for an extended period of time between the pulverizing surfaces. As a result, the material can be ground down into powder having a small grain size.
摘要翻译：用于粉碎茶叶的粉碎机，芝麻和小麦等谷物，以及陶瓷和岩石等矿物质。为粉碎机设置的一对上下砂浆相对于在设置在下砂浆的上表面的粉碎表面和设置在上砂浆的底面上的粉碎表面之间的材料进行粉碎。下砂浆的粉碎表面形成为凹锥形，并且上砂浆的粉碎表面形成为与凹锥形状匹配的圆锥形状。因此，当在上下砂浆的粉碎表面之间进行粉碎时，材料沿着下砂浆的粉碎表面朝向其外周部分升起并沿着粉碎表面向下滑动，朝向其中心部分返回。重复上下运动。因此，材料可以在粉碎表面之间延长一段时间。结果，该材料可以被粉碎成具有小颗粒尺寸的粉末。

3. 发明授权

US5333032A Logic design system and method in the same 失效
标题翻译：逻辑设计系统与方法相同
公开(公告)号：US5333032A
公开(公告)日：1994-07-26
申请号：US667987
申请日：1991-03-12
申请人： Noriko Matsumoto , Shoji Takaoka , Masahiko Ueda , Tamotsu Nishiyama
发明人： Noriko Matsumoto , Shoji Takaoka , Masahiko Ueda , Tamotsu Nishiyama
IPC分类号： H03K19/173 , G06F17/50 , G06F15/60
CPC分类号： G06F17/505
摘要： In a system for transforming input circuit information into information of a logic circuit composed of actual elements, a schematic diagram of a logic circuit composed of actual elements is displayed. A timing check is executed on the displayed logic circuit. A delay adjustment portion of the displayed schematic diagram is designated. A timing adjustment is executed by the system on the designated delay adjustment portion, and thereby the logic circuit is transformed into a second logic circuit composed of actual elements.
摘要翻译：在将输入电路信息变换成由实际元件构成的逻辑电路的信息的系统中，显示由实际元件构成的逻辑电路的示意图。在显示的逻辑电路上执行定时检查。指定所示示意图的延迟调整部分。由系统在指定的延迟调整部分执行定时调整，从而将逻辑电路变换为由实际元件组成的第二逻辑电路。

4. 发明申请

US20080250379A1 LOGIC CIRCUIT SYNTHESIS DEVICE 审中-公开
标题翻译：逻辑电路合成器件
公开(公告)号：US20080250379A1
公开(公告)日：2008-10-09
申请号：US11947417
申请日：2007-11-29
申请人： Shoji TAKAOKA , Atsushi Yamamoto , Tomohiro Tsuda , Takashi Hiramatsu
发明人： Shoji TAKAOKA , Atsushi Yamamoto , Tomohiro Tsuda , Takashi Hiramatsu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In a logic circuit synthesis device, a library of cell preliminarily stores a condition concerning a property that should be satisfied by the net having the property. The logic circuit synthesis device selects, from a list of nets, a net that has a predetermined property. the logic circuit synthesis device performs logic synthesis in accordance with the condition stored in the library, for the selected net.
摘要翻译：在逻辑电路合成装置中，单元库预先存储有关具有该属性的网应满足的属性的条件。逻辑电路合成装置从网络列表中选择具有预定属性的网络。逻辑电路合成装置根据存储在库中的条件对所选网络进行逻辑合成。

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