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1. 发明申请

US20100326954A1 METHOD OF ETCHING A MULTI-LAYER 审中-公开
标题翻译：蚀刻多层的方法
公开(公告)号：US20100326954A1
公开(公告)日：2010-12-30
申请号：US12492152
申请日：2009-06-26
申请人： Zhen Yu Zhuo , Shi Jie Bai
发明人： Zhen Yu Zhuo , Shi Jie Bai
IPC分类号： C23F1/02
CPC分类号： C23F4/00 , H01L21/32136
摘要： A method of etching a multi-layer is provided. The multi-layer includes an aluminum layer disposed on a semiconductor substrate and an anti-reflection coating layer disposed on the aluminum layer. The method includes: performing a first etching process to etch the anti-reflection coating layer by providing a first etching gas, wherein the first etching gas includes a chlorine-containing substance; then performing a second etching process to etch the aluminum layer by providing a second etching gas, wherein the second etching gas does not include a chlorine-containing compound.
摘要翻译：提供蚀刻多层的方法。多层包括设置在半导体衬底上的铝层和设置在铝层上的抗反射涂层。该方法包括：通过提供第一蚀刻气体进行第一蚀刻工艺以蚀刻抗反射涂层，其中第一蚀刻气体包括含氯物质; 然后进行第二蚀刻工艺以通过提供第二蚀刻气体来蚀刻铝层，其中第二蚀刻气体不包括含氯化合物。

2. 发明申请

US20100190272A1 REWORK METHOD OF METAL HARD MASK 审中-公开
标题翻译：金属硬掩模的方法
公开(公告)号：US20100190272A1
公开(公告)日：2010-07-29
申请号：US12358914
申请日：2009-01-23
申请人： Yu Zhang , Bin Zhao , Kah-Lun Toh , Shi-Jie Bai
发明人： Yu Zhang , Bin Zhao , Kah-Lun Toh , Shi-Jie Bai
IPC分类号： H01L21/302 , H01L21/44 , H01L21/02
CPC分类号： H01L21/76802 , H01L21/31144
摘要： A rework method of a metal hard mask layer is provided. First, a material layer is provided. A dielectric layer, a first metal hard mask layer, and a patterned first dielectric hard mask layer have been sequentially formed on the material layer. There is a defect on a region of the first metal hard mask layer, and therefore the region of the first metal hard mask layer is not able to be patterned. After that, the patterned first dielectric hard mask layer and the first metal hard mask layer are removed. A planarization process is then performed on the dielectric layer. Next, a second metal hard mask layer and a second dielectric hard mask layer are sequentially formed on the dielectric layer.
摘要翻译：提供了金属硬掩模层的返工方法。首先，提供材料层。电介质层，第一金属硬掩模层和图案化的第一电介质硬掩模层已顺序地形成在材料层上。在第一金属硬掩模层的区域上存在缺陷，因此第一金属硬掩模层的区域不能被图案化。之后，去除图案化的第一电介质硬掩模层和第一金属硬掩模层。然后在电介质层上进行平坦化处理。接下来，在电介质层上依次形成第二金属硬掩模层和第二电介质硬掩模层。

3. 发明授权

US07622395B2 Two-step method for etching a fuse window on a semiconductor substrate 有权
标题翻译：用于蚀刻半导体衬底上的熔丝窗的两步法
公开(公告)号：US07622395B2
公开(公告)日：2009-11-24
申请号：US11616300
申请日：2006-12-27
申请人： Shi-Jie Bai , Hong Ma
发明人： Shi-Jie Bai , Hong Ma
IPC分类号： H01L21/302
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.
摘要翻译：提供了用于蚀刻半导体衬底上的熔丝窗的两步法。具有熔丝互连线的半导体衬底形成在电介质膜叠层中。电介质膜堆叠包括覆盖所述熔丝互连线的目标介电层，中间介电层和钝化层。在钝化层上形成具有限定所述熔丝窗的开口的光致抗蚀剂层。执行第一干蚀刻工艺以通过开口非选择性地蚀刻钝化层和中间介电层，从而暴露目标介电层。然后测量第一干蚀刻工艺之后的目标介电层的厚度。执行APC控制的第二干蚀刻工艺以蚀刻暴露的目标介电层的一部分，从而可靠地形成熔丝窗。

4. 发明申请

US20110108991A1 CIRCUIT LAYOUT STRUCTURE 有权
标题翻译：电路布局结构
公开(公告)号：US20110108991A1
公开(公告)日：2011-05-12
申请号：US12615276
申请日：2009-11-10
申请人： Ching Long Tsai , Shi Jie Bai , Shan Liu , Yu Zhang
发明人： Ching Long Tsai , Shi Jie Bai , Shan Liu , Yu Zhang
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/31116
摘要： A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal interlayer dielectric layer and the metal interconnect. The metal pattern or the metal interconnect are suitably segregated to reduce a capacitance charging effect.
摘要翻译：电路布局结构包括围绕金属互连的金属层间介质层和擦洗线内的金属图案。擦洗线在金属层间介电层和金属互连附近。适当地分离金属图案或金属互连以减小电容充电效果。

5. 发明申请

US20090023283A1 INTERCONNECTION PROCESS 审中-公开
标题翻译：互连过程
公开(公告)号：US20090023283A1
公开(公告)日：2009-01-22
申请号：US11778844
申请日：2007-07-17
申请人： Hong Ma , Shi-Jie Bai
发明人： Hong Ma , Shi-Jie Bai
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76813
摘要： An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.
摘要翻译：描述互连过程。提供其中形成有导电区域的基板。在基板上形成电介质层。在电介质层上形成具有沟槽开口的图案化金属硬掩模层。电介质硬掩模层在图案化的金属硬掩模层上保形地形成并填充在沟槽开口中。限定光致抗蚀剂图案以去除电介质硬掩模层的一部分和电介质层的一部分以在电介质层中形成第一开口。去除光致抗蚀剂图案。使用图案化的金属硬掩模层作为掩模来执行第一蚀刻工艺以形成沟槽和从介电层中的第一开口向下延伸的第二开口。第二个开口露出导电区域。导电层形成在沟槽和第二开口中。

6. 发明申请

US20080160652A1 TWO-STEP METHOD FOR ETCHING A FUSE WINDOW ON A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：用于在半导体衬底上蚀刻保险丝窗口的两步法
公开(公告)号：US20080160652A1
公开(公告)日：2008-07-03
申请号：US11616300
申请日：2006-12-27
申请人： Shi-Jie Bai , Hong Ma
发明人： Shi-Jie Bai , Hong Ma
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.
摘要翻译：提供了用于蚀刻半导体衬底上的熔丝窗的两步法。具有熔丝互连线的半导体衬底形成在电介质膜叠层中。电介质膜堆叠包括覆盖所述熔丝互连线的目标介电层，中间介电层和钝化层。在钝化层上形成具有限定所述熔丝窗的开口的光致抗蚀剂层。执行第一干蚀刻工艺以通过开口非选择性地蚀刻钝化层和中间介电层，从而暴露目标介电层。然后测量第一干蚀刻工艺之后的目标介电层的厚度。执行APC控制的第二干蚀刻工艺以蚀刻暴露的目标介电层的一部分，从而可靠地形成熔丝窗。

7. 发明授权

US08278761B2 Circuit layout structure 有权
标题翻译：电路布局结构
公开(公告)号：US08278761B2
公开(公告)日：2012-10-02
申请号：US12615276
申请日：2009-11-10
申请人： Ching Long Tsai , Shi Jie Bai , Shan Liu , Yu Zhang
发明人： Ching Long Tsai , Shi Jie Bai , Shan Liu , Yu Zhang
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/31116
摘要： A circuit layout structure includes a metal interlayer dielectric layer surrounding a metal interconnect and a metal pattern within a scrub line. The scrub line is in the vicinity of the metal interlayer dielectric layer and the metal interconnect. The metal pattern or the metal interconnect are suitably segregated to reduce a capacitance charging effect.
摘要翻译：电路布局结构包括围绕金属互连的金属层间介质层和擦洗线内的金属图案。擦洗线在金属层间介电层和金属互连附近。适当地分离金属图案或金属互连以减小电容充电效果。

8. 发明授权

US08110342B2 Method for forming an opening 有权
标题翻译：形成开口的方法
公开(公告)号：US08110342B2
公开(公告)日：2012-02-07
申请号：US12193052
申请日：2008-08-18
申请人： Feng Liu , Shi-Jie Bai , Hong Ma , Chun-Peng Ng , Ye Wang
发明人： Feng Liu , Shi-Jie Bai , Hong Ma , Chun-Peng Ng , Ye Wang
IPC分类号： G03F7/26
CPC分类号： H01L21/76802 , H01L21/76804 , H01L21/76811 , H01L21/76813
摘要： A method for forming an opening is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes at least one metal interconnects therein. A stacked film is formed on the semiconductor substrate, in which the stacked film includes at least one dielectric layer and one hard mask. The hard mask is used to form an opening in the stacked film without exposing the metal interconnects, and the hard mask is removed thereafter. A barrier layer is later deposited on the semiconductor substrate to cover a portion of the dielectric layer and the surface of the metal interconnects.
摘要翻译：公开了一种形成开口的方法。首先，提供半导体衬底，其中半导体衬底在其中包括至少一个金属互连。层叠膜形成在半导体基板上，其中层叠膜包括至少一个电介质层和一个硬掩模。硬掩模用于在不暴露金属互连件的情况下在堆叠膜中形成开口，并且之后去除硬掩模。稍后在半导体衬底上沉积阻挡层以覆盖电介质层的一部分和金属互连的表面。

9. 发明授权

US07704870B2 Via-first interconnection process using gap-fill during trench formation 有权
标题翻译：在沟槽形成期间使用间隙填充的通过第一互连工艺
公开(公告)号：US07704870B2
公开(公告)日：2010-04-27
申请号：US12179838
申请日：2008-07-25
申请人： Hong Ma , Shi-Jie Bai
发明人： Hong Ma , Shi-Jie Bai
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76813
摘要： An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening.
摘要翻译：描述互连过程。提供其中形成有导电区域的基板。在基板上形成电介质层。在电介质层上形成具有沟槽开口的图案化金属硬掩模层。电介质硬掩模层在图案化的金属硬掩模层上保形地形成并填充在沟槽开口中。限定光致抗蚀剂图案以去除电介质硬掩模层的一部分和电介质层的一部分以在电介质层中形成第一开口。去除光致抗蚀剂图案。使用图案化的金属硬掩模层作为掩模来执行第一蚀刻工艺以形成沟槽和从介电层中的第一开口向下延伸的第二开口。第二个开口露出导电区域。导电层形成在沟槽和第二开口中。

10. 发明申请

US20100040982A1 METHOD FOR FORMING AN OPENING 有权
标题翻译：形成开放的方法
公开(公告)号：US20100040982A1
公开(公告)日：2010-02-18
申请号：US12193052
申请日：2008-08-18
申请人： Feng Liu , Shi-Jie Bai , Hong Ma , Chun-Peng Ng , Ye Wang
发明人： Feng Liu , Shi-Jie Bai , Hong Ma , Chun-Peng Ng , Ye Wang
IPC分类号： G03F7/20
CPC分类号： H01L21/76802 , H01L21/76804 , H01L21/76811 , H01L21/76813
摘要： A method for forming an opening is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes at least one metal interconnects therein. A stacked film is formed on the semiconductor substrate, in which the stacked film includes at least one dielectric layer and one hard mask. The hard mask is used to form an opening in the stacked film without exposing the metal interconnects, and the hard mask is removed thereafter. A barrier layer is later deposited on the semiconductor substrate to cover a portion of the dielectric layer and the surface of the metal interconnects.
摘要翻译：公开了一种形成开口的方法。首先，提供半导体衬底，其中半导体衬底在其中包括至少一个金属互连。层叠膜形成在半导体基板上，其中层叠膜包括至少一个电介质层和一个硬掩模。硬掩模用于在不暴露金属互连件的情况下在堆叠膜中形成开口，并且之后去除硬掩模。稍后在半导体衬底上沉积阻挡层以覆盖电介质层的一部分和金属互连的表面。

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