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1. 发明授权

US07082069B2 Memory array with fast bit line precharge 有权
标题翻译：具有快速位线预充电的存储器阵列
公开(公告)号：US07082069B2
公开(公告)日：2006-07-25
申请号：US11004148
申请日：2004-12-03
申请人： Sheree Chou , Lung-Feng Lin , Yu-Shen Lin
发明人： Sheree Chou , Lung-Feng Lin , Yu-Shen Lin
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C16/26 , G11C7/12
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.
摘要翻译：提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。预充电晶体管耦合到阵列中的相应位线，并且适于将各个位线上的电压预充电到接近目标电平。检测器具有耦合到参考位线的输入端和耦合到多个位线上的预充电晶体管的输出。当参考位线具有接近目标电平的电压时，检测器产生预充电晶体管，当基准位线具有低于目标电平的电压时，该预充电信号导通预充电晶体管。

2. 发明申请

US20060120175A1 MEMORY ARRAY WITH FAST BIT LINE PRECHARGE 有权
标题翻译：存储器阵列与快速位线预置
公开(公告)号：US20060120175A1
公开(公告)日：2006-06-08
申请号：US11004148
申请日：2004-12-03
申请人： Sheree Chou , Yung-Feng Lin , Yu-Shen Lin
发明人： Sheree Chou , Yung-Feng Lin , Yu-Shen Lin
IPC分类号： G11C7/10
CPC分类号： G11C16/26 , G11C7/12
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.
摘要翻译：提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。预充电晶体管耦合到阵列中的相应位线，并且适于将各个位线上的电压预充电到接近目标电平。检测器具有耦合到参考位线的输入端和耦合到多个位线上的预充电晶体管的输出。当参考位线具有接近目标电平的电压时，检测器产生预充电晶体管，当基准位线具有低于目标电平的电压时，该预充电信号导通预充电晶体管。

3. 发明申请

US20060120174A1 MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE 有权
标题翻译：低功率位线前置存储器阵列
公开(公告)号：US20060120174A1
公开(公告)日：2006-06-08
申请号：US11003092
申请日：2004-12-03
申请人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
发明人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C16/24
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
摘要翻译：提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。夹持晶体管耦合到阵列中的相应位线，并且适于防止相应位线上的电压超过目标电平。比较器具有耦合到参考位线的输入端和耦合到多个位线上的钳位晶体管的输出。比较器产生偏置电压，当参考位线具有低于目标电平的电压时，将钳位晶体管导通到第一偏置电平，并且当参考位线具有接近目标水平的电压。

4. 发明授权

US07082061B2 Memory array with low power bit line precharge 有权
标题翻译：具有低功耗位线预充电的存储器阵列
公开(公告)号：US07082061B2
公开(公告)日：2006-07-25
申请号：US11003092
申请日：2004-12-03
申请人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
发明人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/12 , G11C16/24
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
摘要翻译：提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。夹持晶体管耦合到阵列中的相应位线，并且适于防止相应位线上的电压超过目标电平。比较器具有耦合到参考位线的输入端和耦合到多个位线上的钳位晶体管的输出。比较器产生偏置电压，当参考位线具有低于目标电平的电压时，将钳位晶体管导通到第一偏置电平，并且当参考位线具有接近目标水平的电压。

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