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1. 发明申请

US20060120174A1 MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE 有权
标题翻译：低功率位线前置存储器阵列
公开(公告)号：US20060120174A1
公开(公告)日：2006-06-08
申请号：US11003092
申请日：2004-12-03
申请人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
发明人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C16/24
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
摘要翻译：提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。夹持晶体管耦合到阵列中的相应位线，并且适于防止相应位线上的电压超过目标电平。比较器具有耦合到参考位线的输入端和耦合到多个位线上的钳位晶体管的输出。比较器产生偏置电压，当参考位线具有低于目标电平的电压时，将钳位晶体管导通到第一偏置电平，并且当参考位线具有接近目标水平的电压。

2. 发明申请

US20060104098A1 Voltage-regulating device for charge pump 有权
标题翻译：电荷泵电压调节装置
公开(公告)号：US20060104098A1
公开(公告)日：2006-05-18
申请号：US11286204
申请日：2005-11-23
申请人： Lung-Yi Chueh , Yu-Shen Lin
发明人： Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： H02M3/18
CPC分类号： H02M3/073 , H02M1/143 , H02M1/15 , H02M2003/075
摘要： A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.
摘要翻译：公开了一种用于电荷泵的电压调节装置。电荷泵根据至少一个时钟信号的工作输出输出电压。电压调节装置至少包括一个电压调节电容器和至少一个逆变器。逆变器用于接收时钟信号并相应地输出反相时钟信号。电压调节电容器具有耦合到输出电压的一个端子，而耦合到反相器的另一个端子用于接收逆时钟信号。 PMOS晶体管的宽度与逆变器中的NMOS晶体管的宽度不同。

3. 发明授权

US07227764B2 Voltage-regulating device for charge pump 有权
标题翻译：电荷泵电压调节装置
公开(公告)号：US07227764B2
公开(公告)日：2007-06-05
申请号：US11286204
申请日：2005-11-23
申请人： Lung-Yi Chueh , Yu-Shen Lin
发明人： Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： H02M3/18 , H02M3/02
CPC分类号： H02M3/073 , H02M1/143 , H02M1/15 , H02M2003/075
摘要： A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.
摘要翻译：公开了一种用于电荷泵的电压调节装置。电荷泵根据至少一个时钟信号的工作输出输出电压。电压调节装置至少包括一个电压调节电容器和至少一个逆变器。逆变器用于接收时钟信号并相应地输出反相时钟信号。电压调节电容器具有耦合到输出电压的一个端子，而耦合到反相器的另一个端子用于接收逆时钟信号。 PMOS晶体管的宽度与逆变器中的NMOS晶体管的宽度不同。

4. 发明授权

US07082061B2 Memory array with low power bit line precharge 有权
标题翻译：具有低功耗位线预充电的存储器阵列
公开(公告)号：US07082061B2
公开(公告)日：2006-07-25
申请号：US11003092
申请日：2004-12-03
申请人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
发明人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/12 , G11C16/24
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
摘要翻译：提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。夹持晶体管耦合到阵列中的相应位线，并且适于防止相应位线上的电压超过目标电平。比较器具有耦合到参考位线的输入端和耦合到多个位线上的钳位晶体管的输出。比较器产生偏置电压，当参考位线具有低于目标电平的电压时，将钳位晶体管导通到第一偏置电平，并且当参考位线具有接近目标水平的电压。

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