专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08159853B2 Memory module cutting off DM pad leakage current 有权
标题翻译：内存模块切断DM焊盘漏电流
公开(公告)号：US08159853B2
公开(公告)日：2012-04-17
申请号：US12693010
申请日：2010-01-25
申请人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
发明人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
IPC分类号： G11C5/02
CPC分类号： G11C7/1078 , G11C5/06 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.
摘要翻译：存储器模块包括：存储器件上的ODT电路，并且包括连接在上拉和下拉晶体管之间的上拉和下拉电阻。在模块板的抽头区域中提供数据屏蔽（DM）焊盘。还提供电流泄漏监测单元并接收来自DM焊盘的基态信号和来自存储器件的位配置信号，并禁止上拉晶体管截止ODT电路的上拉电阻之间的电流通路和ODT使能模式下的DM焊盘。

2. 发明申请

US20070022335A1 Methods and apparatus for interfacing between test system and memory 失效
标题翻译：用于测试系统和存储器之间接口的方法和设备
公开(公告)号：US20070022335A1
公开(公告)日：2007-01-25
申请号：US11517259
申请日：2006-09-08
申请人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung-Hee Han
发明人： Seung-Man Shin , Seung-Jin Seo , You-Keun Han , Hui-Chong Shin , Jong-Geon Lee , Kyung-Hee Han
IPC分类号： G11C29/00
CPC分类号： G06F11/267
摘要： Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.
摘要翻译：提供了将至少一个存储器进入测试模式的方法和装置。至少一个测试MRS位可以存储在用于控制存储器的第一寄存器中。至少一个测试MRS代码可以被编程到第二个寄存器中。存储在第一寄存器中的至少一个比特中的每一个可以对应于存储在第二寄存器中的至少一个测试MRS码之一。

3. 发明申请

US20060280024A1 Memory system with registered memory module and control method 失效
标题翻译：具有注册内存模块和控制方法的内存系统
公开(公告)号：US20060280024A1
公开(公告)日：2006-12-14
申请号：US11254696
申请日：2005-10-21
申请人： Young-Man Ahn , Seung-Jin Seo , Seung-Hee Mun , Jong-Cheol Seo , Jung-Kuk Lee , Soon-Deok Jang
发明人： Young-Man Ahn , Seung-Jin Seo , Seung-Hee Mun , Jong-Cheol Seo , Jung-Kuk Lee , Soon-Deok Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal clock signals. The register stores an external control/address signal in response to the first internal clock signal and transmits an internal control/address signal derived from the external control/address in response to the second internal control/address signal.
摘要翻译：公开了一种存储器模块及相关方法。存储器模块包括被配置为相对于外部时钟信号产生第一和第二内部时钟信号的时钟发生器以及被配置为接收第一和第二内部时钟信号的寄存器。寄存器响应于第一内部时钟信号存储外部控制/地址信号，并响应于第二内部控制/地址信号发送从外部控制/地址导出的内部控制/地址信号。

4. 发明申请

US20060006419A1 Method of testing a memory module and hub of the memory module 失效
公开(公告)号：US20060006419A1
公开(公告)日：2006-01-12
申请号：US11118377
申请日：2005-05-02
申请人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
发明人： Seung-Man Shin , Byung-Se So , Seung-Jin Seo , You-Keun Han
IPC分类号： H01L31/109
CPC分类号： G11C29/08 , G11C5/04 , G11C2029/5602
摘要： A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.

5. 发明授权

US08462534B2 Memory module cutting off DM pad leakage current 有权
标题翻译：内存模块切断DM焊盘漏电流
公开(公告)号：US08462534B2
公开(公告)日：2013-06-11
申请号：US13430860
申请日：2012-03-27
申请人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
发明人： Seok-Il Kim , You-Keun Han , Seung-Jin Seo
IPC分类号： G11C5/02
CPC分类号： G11C7/1078 , G11C5/06 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.
摘要翻译：存储器模块包括：存储器件上的ODT电路，并且包括连接在上拉和下拉晶体管之间的上拉和下拉电阻。在模块板的抽头区域中提供数据屏蔽（DM）焊盘。还提供电流泄漏监测单元并接收来自DM焊盘的基态信号和来自存储器件的位配置信号，并禁止上拉晶体管截止ODT电路的上拉电阻之间的电流通路和ODT使能模式下的DM焊盘。

6. 发明申请

US20120182777A1 MEMORY MODULE CUTTING OFF DM PAD LEAKAGE CURRENT 有权
标题翻译：存储器模块切断DM PAD泄漏电流
公开(公告)号：US20120182777A1
公开(公告)日：2012-07-19
申请号：US13430860
申请日：2012-03-27
申请人： Seok-Il KIM , You-Keun HAN , Seung-Jin SEO
发明人： Seok-Il KIM , You-Keun HAN , Seung-Jin SEO
IPC分类号： G11C5/02
CPC分类号： G11C7/1078 , G11C5/06 , G11C7/1084 , G11C11/4093 , G11C2207/105
摘要： A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.
摘要翻译：存储器模块包括：存储器件上的ODT电路，并且包括连接在上拉和下拉晶体管之间的上拉和下拉电阻。在模块板的抽头区域中提供数据屏蔽（DM）焊盘。还提供电流泄漏监测单元并接收来自DM焊盘的基态信号和来自存储器件的位配置信号，并禁止上拉晶体管截止ODT电路的上拉电阻之间的电流通路和ODT使能模式下的DM焊盘。

7. 发明授权

US07930465B2 Determining operation mode for semiconductor memory device 有权
标题翻译：确定半导体存储器件的工作模式
公开(公告)号：US07930465B2
公开(公告)日：2011-04-19
申请号：US11256580
申请日：2005-10-21
申请人： Seok-Il Kim , Young-Man Ahn , Byung-Se So , Seung-Jin Seo
发明人： Seok-Il Kim , Young-Man Ahn , Byung-Se So , Seung-Jin Seo
IPC分类号： G06F12/00
CPC分类号： G11C29/46 , G11C11/401
摘要： A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.
摘要翻译：公开了能够通过使用数据引脚的状态来确定操作模式的半导体存储器件及其操作模式确定方法。半导体存储器件包括至少一个MRS输入焊盘，至少一个数据输入焊盘和操作模式确定电路。当通过MRS输入焊盘输入的MRS命令对应于预定的MRS命令并且通过数据输入焊盘或焊盘输入的数据信号包括预定的组合时，操作模式确定电路产生操作模式确定信号。因此，可以通过在模块组装过程中确定半导体存储器件的操作模式来改善制造和制造工艺中的效率。

8. 发明申请

US20100169725A1 MEMORY MODULE TESTER 审中-公开
标题翻译：内存模块测试仪
公开(公告)号：US20100169725A1
公开(公告)日：2010-07-01
申请号：US12648588
申请日：2009-12-29
申请人： Jung Kuk Lee , Seung Hee Mun , Seung Jin Seo , Woo-Jin Na
发明人： Jung Kuk Lee , Seung Hee Mun , Seung Jin Seo , Woo-Jin Na
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/56 , G11C5/04
摘要： a memory module test system for testing a plurality of memory modules includes a plurality buffers in one-to-one correspondence the plurality of memory modules, each of the buffers including a self-test engine for testing a corresponding memory module. The test system further includes an interface configured to receive a test program for testing the memory module, and a gate array configured to transmit the test program to the buffers using a Joint Test Action Group (JTAG) protocol and to read test results of the test program from the buffers using the JTAG protocol.
摘要翻译：用于测试多个存储器模块的存储器模块测试系统包括多个缓冲器，该多个缓冲器与多个存储器模块一一对应，每个缓冲器包括用于测试相应的存储器模块的自检引擎。测试系统还包括被配置为接收用于测试存储器模块的测试程序的接口以及配置成使用联合测试动作组（JTAG）协议将测试程序发送到缓冲器并且读取测试结果的门阵列使用JTAG协议从缓冲区编程。

9. 发明授权

US07539910B2 Memory module test system for memory module including hub 失效
标题翻译：内存模块测试系统，内存模块包括集线器
公开(公告)号：US07539910B2
公开(公告)日：2009-05-26
申请号：US10900140
申请日：2004-07-28
申请人： Young-Man Ahn , Byung-Se So , Seung-Jin Seo , Seung-Man Shin
发明人： Young-Man Ahn , Byung-Se So , Seung-Jin Seo , Seung-Man Shin
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C29/48 , G11C29/56012 , G11C2029/5602
摘要： A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.
摘要翻译：一种包括至少一个存储器模块的存储器模块测试系统。所述至少一个存储器模块包括第一集线器和多个半导体存储器件。该系统包括用于测试至少一个存储器模块的测试器。第二集线器位于第一集线器和测试仪之间。第二集线器用于将从测试器输出的存储器命令和存储器数据转换成分组数据，并将分组数据发送到第一集线器。第二集线器将从第一集线器输出的分组数据转换为存储器数据，并将存储器数据发送到测试器。

10. 发明申请

US20090103374A1 MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME 有权
标题翻译：具有相同模式的存储器模块和存储器系统
公开(公告)号：US20090103374A1
公开(公告)日：2009-04-23
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
发明人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式