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    • 1. 发明授权
    • Method and apparatus for high-speed input sampling
    • 高速输入采样方法和装置
    • US07366942B2
    • 2008-04-29
    • US10918008
    • 2004-08-12
    • Seonghoon Lee
    • Seonghoon Lee
    • G06F1/04
    • H03K5/135G11C27/02
    • A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
    • 公开了用于信号的高速输入采样的信号采样器和方法。 第一采样器在时钟信号的上升沿采样数据信号并产生第一采样信号。 第二采样器在反相时钟信号的下降沿采样数据信号,并产生第二采样信号。 可以组合第一和第二采样信号以确定下一个信号采样器输出。 如果第一和第二采样信号被断言,评估可以包括断言输出信号,如果第一和第二采样信号被否定则否定输出信号,如果第一和第二采样信号处于相反的逻辑状态,则转换输出信号。 信号采样器和信号采样方法可以结合在半导体器件中,半导体器件可以制造在半导体晶片上并且被包括在电子系统中。
    • 3. 发明授权
    • Method and apparatus of high-speed input sampling
    • 高速输入采样方法和装置
    • US07747890B2
    • 2010-06-29
    • US11590582
    • 2006-10-31
    • Seonghoon Lee
    • Seonghoon Lee
    • G06F1/04
    • H03K5/135G11C27/02
    • A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signals are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
    • 公开了用于信号的高速输入采样的信号采样器和方法。 第一采样器在时钟信号的上升沿采样数据信号并产生第一采样信号。 第二采样器在反相时钟信号的下降沿采样数据信号,并产生第二采样信号。 可以组合第一和第二采样信号以确定下一个信号采样器输出。 如果第一和第二采样信号被断言,评估可以包括断言输出信号,如果第一和第二采样信号被否定则否定输出信号,如果第一和第二采样信号处于相反的逻辑状态,则转换输出信号。 信号采样器和信号采样方法可以结合在半导体器件中,半导体器件可以制造在半导体晶片上并且被包括在电子系统中。
    • 4. 发明授权
    • Method and apparatus for timing domain crossing
    • 时域交叉的方法和装置
    • US07375560B2
    • 2008-05-20
    • US11495848
    • 2006-07-28
    • Seonghoon LeeJ. Brian Johnson
    • Seonghoon LeeJ. Brian Johnson
    • H03L7/00
    • G11C11/4076G11C7/1066G11C7/1072G11C7/1078G11C7/1087G11C7/1093G11C7/22G11C7/222G11C11/4093
    • A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
    • 公开了一种在定时域之间传送信号的定时域交叉装置和方法。 接收机用第一定时域中的采样时钟对数据信号进行采样。 采样的数据信号被扩展成多个扩展信号,这些扩展信号在多个连续的活动时钟周期中保持有效。 数据顺序调整器可以将多个扩展信号重新排序到预定的顺序。 定时发生器用第二定时域中的内部时钟对命令信号进行采样以产生重新定时选通。 重新定时选通可以在时间上位于扩展数据窗口内,并用于在第二定时域中采样多个扩展信号。 信号采样的定时域交叉装置和方法可以结合在半导体器件中,半导体器件可以制造在半导体晶片上并且被包括在电子系统中。
    • 7. 发明申请
    • Method and apparatus of high-speed input sampling
    • 高速输入采样方法和装置
    • US20070046515A1
    • 2007-03-01
    • US11590582
    • 2006-10-31
    • Seonghoon Lee
    • Seonghoon Lee
    • H03M1/00
    • H03K5/135G11C27/02
    • A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
    • 公开了用于信号的高速输入采样的信号采样器和方法。 第一采样器在时钟信号的上升沿采样数据信号并产生第一采样信号。 第二采样器在反相时钟信号的下降沿采样数据信号,并产生第二采样信号。 可以组合第一和第二采样信号以确定下一个信号采样器输出。 如果第一和第二采样信号被断言,评估可以包括断言输出信号,如果第一和第二采样信号被否定则否定输出信号,如果第一和第二采样信号处于相反的逻辑状态,则转换输出信号。 信号采样器和信号采样方法可以结合在半导体器件中,半导体器件可以制造在半导体晶片上并且被包括在电子系统中。