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1. 发明授权

US08957721B2 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US08957721B2
公开(公告)日：2015-02-17
申请号：US14345452
申请日：2012-07-27
申请人： Seiichiro Kihara , Shunichi Utsumi
发明人： Seiichiro Kihara , Shunichi Utsumi
IPC分类号： H03L5/00 , H03K3/013 , H03K3/356 , H03K19/0185 , H03K19/00
CPC分类号： H03K3/013 , H03K3/356 , H03K3/356069 , H03K19/0013 , H03K19/018507
摘要： The present invention provides a level shift circuit having low possibility of malfunction by noise, and can operate with low power. A level shift circuit 1 includes first and second MOSFETs 12a and 12b using signals with phases same as and opposite to the phase of an input signal Sin as gate inputs, first and second resistance elements 13a and 13b, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second MOSFETs, a comparator 14 having a pair of differential input terminals, which are individually connected to respective drains of the first and second MOSFETs, and a current control circuit 16 that controls an amount of first current flowing through the first MOSFET via the first resistance element and an amount of second current flowing through the second MOSFET via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.
摘要翻译：本发明提供了具有低噪声故障可能性低的电平移位电路，并且能够以低功率工作。电平移位电路1包括使用与作为栅极输入的输入信号Sin的相位相同且相反的相位的信号的第一和第二MOSFET 12a和12b，第一和第二电阻元件13a和13b，其一端连接到移位电平电源端子，其提供电平移位输出信号的高电平输出电压，并且每个具有连接到第一和第二MOSFET的相应漏极的另一端;具有一对差分输入端子的比较器14，其分别连接到第一和第二MOSFET的各自的漏极，以及电流控制电路16，其控制经由第一电阻元件流过第一MOSFET的第一电流量和经由第二电阻元件流过第二MOSFET的第二电流量与输入信号的信号电平的上升和下降同步。

2. 发明申请

US20130200926A1 DRIVER CIRCUIT 有权
标题翻译：驱动电路
公开(公告)号：US20130200926A1
公开(公告)日：2013-08-08
申请号：US13879940
申请日：2011-07-25
申请人： Seiichiro Kihara , Akio Nakajima
发明人： Seiichiro Kihara , Akio Nakajima
IPC分类号： H03K17/687
CPC分类号： H03K17/687 , H03K17/063 , H03K17/6871 , H03K2017/066 , H03K2017/6875 , H03K2217/0081
摘要： A gate driver circuit that can supply a negative gate voltage to a high-side circuit without being additionally provided with an insulated power supply is realized. A driver circuit is configured such that a half-bridge circuit in which a first transistor and a second transistor are connected in series includes a capacitor that supplies a negative gate voltage to a high-side first transistor via a first control circuit, and a control circuit power supply that supplies a negative gate voltage to a low-side second transistor via a second control circuit, one end of the capacitor being connected to a negative voltage VEE on a negative terminal side of the control circuit power supply via a switching element, and the other end being connected to a voltage on an output terminal, wherein the switching element is controlled to be on upon a timing when the second transistor is turned on.
摘要翻译：实现了可以向高边电路提供负栅极电压而不额外设置绝缘电源的栅极驱动电路。驱动电路被配置为使得第一晶体管和第二晶体管串联连接的半桥电路包括经由第一控制电路向高侧第一晶体管提供负栅极电压的电容器，以及控制电路电源，经由第二控制电路向低侧第二晶体管提供负栅极电压，电容器的一端经由开关元件连接到控制电路电源的负极侧的负电压VEE，并且另一端连接到输出端子上的电压，其中在第二晶体管导通的定时将开关元件控制为导通。

3. 发明授权

US4988895A Comparator circuit 失效
标题翻译：比较器电路
公开(公告)号：US4988895A
公开(公告)日：1991-01-29
申请号：US541211
申请日：1990-06-22
申请人： Seiichiro Kihara , Zenpei Tani , Hisao Nagao
发明人： Seiichiro Kihara , Zenpei Tani , Hisao Nagao
IPC分类号： H03K5/08 , H03K3/0233 , H03K17/30 , H03K5/153 , H03K5/24
CPC分类号： H03K17/30 , H03K3/02337
摘要： A novel comparator circuit is disclosed, in which a pulse output is obtained from the output terminal of a differential amplifier through a transistor by applying a threshold voltage to either input terminal of a differential amplifier composed of a pair of transistors and then comparing an input voltage applied to the other input terminal therewith, wherein the aforementioned pair of transistors of the differential amplifier are each composed of two transistors connected in a complex manner, the input voltage is directly inputted, without the use of a buffer or the like, by raising the input impedance of the comparator circuit to thereby simplify the circuit as a whole and to widen its scope of application. Further, the output terminal of the differential amplifier connected to a transistor in an output circuit of the comparator circuit and a power source are connected through a resistor so as to ensure against occurrence of impulses in the output pulses through prevention of operation of the output circuit alone before changing of the threshold voltage for causing a hysteresis property to be imparted to the comparator circuit.
摘要翻译：公开了一种新颖的比较器电路，其中通过对由晶体管组成的差分放大器的输入端施加阈值电压，然后将输入电压进行比较，通过晶体管从差分放大器的输出端获得脉冲输出应用于其他输入端子，其中差分放大器的上述一对晶体管各自由以复合方式连接的两个晶体管组成，直接输入输入电压，而不需要使用缓冲器等，通过提高比较器电路的输入阻抗，从而简化整个电路并扩大其应用范围。此外，连接到比较器电路的输出电路中的晶体管和电源的差分放大器的输出端子通过电阻器连接，以便通过防止输出电路的操作来确保不会在输出脉冲中产生脉冲在改变阈值电压之前单独地将滞后特性赋予比较器电路。

4. 发明授权

US08971071B2 Driver circuit and inverter circuit 有权
标题翻译：驱动电路和逆变电路
公开(公告)号：US08971071B2
公开(公告)日：2015-03-03
申请号：US13882531
申请日：2011-09-26
申请人： Seiichiro Kihara
发明人： Seiichiro Kihara
IPC分类号： H02H7/122 , H03B1/00 , H03K3/00 , H02M7/5387 , H03K17/06 , H02H3/20 , H02M1/32 , H02M1/38 , H03K17/687
CPC分类号： H02H7/1222 , H02H3/20 , H02M1/32 , H02M1/38 , H02M7/5387 , H03K17/063 , H03K2017/066 , H03K2017/6875
摘要： The present invention provides a safe circuit that can prevent an arm short, when a half-bridge circuit is configured by using a normally-on switching element, and the half-bridge circuit is used as a driver circuit or an inverter circuit. In a driver circuit configured by a half-bridge circuit in which one of input and output terminals of a first switching element 14 is connected to a first power-supply voltage V1 on a high-voltage side, and the first switching element 14 and a second switching element 15 are connected in series, a normally-off third switching element 16 is inserted between the second switching element 15 and a second power-supply voltage V2 on a low voltage side. The third switching element 16 is turned off, when an operating voltage VH or VL supplied from control-circuit power supplies 13a and 13b is insufficient for the operation of a control circuit 11.
摘要翻译：本发明提供了一种安全电路，其可以通过使用常开开关元件来配置半桥电路，并且半桥电路用作驱动电路或逆变器电路，从而可以防止臂短路。在由半桥电路构成的驱动电路中，第一开关元件14的输入端和输出端之一与高电压侧的第一电源电压V1连接，第一开关元件14和第二开关元件15串联连接，在第二开关元件15和低压侧的第二电源电压V2之间插入常关的第三开关元件16。当从控制电路电源13a和13b提供的工作电压VH或VL对于控制电路11的操作不足时，第三开关元件16断开。

5. 发明授权

US08952730B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US08952730B2
公开(公告)日：2015-02-10
申请号：US13879940
申请日：2011-07-25
申请人： Seiichiro Kihara , Akio Nakajima
发明人： Seiichiro Kihara , Akio Nakajima
IPC分类号： H03K3/00 , H03K17/687 , H03K17/06
CPC分类号： H03K17/687 , H03K17/063 , H03K17/6871 , H03K2017/066 , H03K2017/6875 , H03K2217/0081
摘要： A gate driver circuit that can supply a negative gate voltage to a high-side circuit without being additionally provided with an insulated power supply is realized. A driver circuit is configured such that a half-bridge circuit in which a first transistor and a second transistor are connected in series includes a capacitor that supplies a negative gate voltage to a high-side first transistor via a first control circuit, and a control circuit power supply that supplies a negative gate voltage to a low-side second transistor via a second control circuit, one end of the capacitor being connected to a negative voltage VEE on a negative terminal side of the control circuit power supply via a switching element, and the other end being connected to a voltage on an output terminal, wherein the switching element is controlled to be on upon a timing when the second transistor is turned on.
摘要翻译：实现了可以向高边电路提供负栅极电压而不额外设置绝缘电源的栅极驱动电路。驱动电路被配置为使得第一晶体管和第二晶体管串联连接的半桥电路包括经由第一控制电路向高侧第一晶体管提供负栅极电压的电容器，以及控制电路电源，经由第二控制电路向低侧第二晶体管提供负栅极电压，电容器的一端经由开关元件连接到控制电路电源的负极侧的负电压VEE，并且另一端连接到输出端子上的电压，其中在第二晶体管导通的定时将开关元件控制为导通。

6. 发明申请

US20140347116A1 LEVEL SHIFT CIRCUIT 有权
标题翻译：水平移位电路
公开(公告)号：US20140347116A1
公开(公告)日：2014-11-27
申请号：US14345452
申请日：2012-07-27
申请人： Seiichiro Kihara , Shunichi Utsumi
发明人： Seiichiro Kihara , Shunichi Utsumi
IPC分类号： H03K3/013 , H03K19/0185 , H03K19/00 , H03K3/356
CPC分类号： H03K3/013 , H03K3/356 , H03K3/356069 , H03K19/0013 , H03K19/018507
摘要： A level shift circuit of an embodiment includes first and second MOSFETs using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second MOSFETs; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second MOSFETs; and a current control circuit that controls an amount of first current flowing through the first MOSFET via the first resistance element and an amount of second current flowing through the second MOSFET via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.
摘要翻译：实施例的电平移位电路包括使用与作为栅极输入的输入信号的相位相同且相反的信号的第一和第二MOSFET; 第一和第二电阻元件，每个电阻元件的一端连接到提供电平移位输出信号的高电平输出电压的移位电平电源端子，并且每个端子的另一端连接到第一和第二MOSFET的相应漏极; 比较器，具有分别连接到第一和第二MOSFET的相应漏极的一对差动输入端子; 以及电流控制电路，其经由所述第一电阻元件控制流过所述第一MOSFET的第一电流量，以及与所述第二电阻元件的信号电平的上升和下降同步地经由所述第二电阻元件流过所述第二MOSFET的第二电流量的输入信号。

7. 发明申请

US20070083731A1 Processor automatically performing processor ID setting and path setting and method of configuring multiprocessor 审中-公开
标题翻译：处理器自动执行处理器ID设置和路径设置以及配置多处理器的方法
公开(公告)号：US20070083731A1
公开(公告)日：2007-04-12
申请号：US11522986
申请日：2006-09-19
申请人： Seiichiro Kihara
发明人： Seiichiro Kihara
IPC分类号： G06F15/00
CPC分类号： G06F15/7832 , G06F15/8007
摘要： An ID determining portion determines a self processor ID according to an input port name receiving a control instruction and a sender processor ID stored in the received control instruction. The control instruction storing the self processor ID is output from each output port via a diverging portion. Therefore, the processor ID of each processor can be automatically determined during initializing processing.
摘要翻译： ID确定部分根据接收到控制指令的输入端口名称和存储在接收到的控制指令中的发送器处理器ID来确定自身处理器ID。存储自身处理器ID的控制指令通过发散部分从每个输出端口输出。因此，可以在初始化处理期间自动确定每个处理器的处理器ID。

8. 发明授权

US4943736A Waveform converting apparatus 失效
标题翻译：波形转换装置
公开(公告)号：US4943736A
公开(公告)日：1990-07-24
申请号：US301581
申请日：1989-01-26
申请人： Seiichiro Kihara , Naonori Okabayashi
发明人： Seiichiro Kihara , Naonori Okabayashi
IPC分类号： G05F3/26 , H03K5/08
CPC分类号： G05F3/265 , H03K5/082
摘要： A waveform converting apparatus includes a first and a second common-emitter type transistors as part of a first and second emitter follower circuits respectively. The follower circuits are used for converting the impedances of an input signal independently. A first constant current supply is connected to the emitter of the first transistor provided in the first emitter follower circuit, and a second constant current supply is connected to the emitter of the second transistor provided in the second emitter follower circuit. The constant current flowing in the first emitter follower circuit is adjusted to be of a smaller value than the constant current flowing in the second emitter follower circuit. With this difference in current value there is a difference between the base-emitter voltage of the first transistor in the first emitter follower circuit and the base-emitter voltage of the second transistor in the second emitter follower circuit on the basis of the ratio of the first and second constant currents mentioned above. Also with the above described difference in currents a ceramic chip capacitor can be used in an integrating circuit of the converting apparatus.
摘要翻译：波形转换装置分别包括作为第一和第二射极跟随器电路的一部分的第一和第二共发射极型晶体管。跟随器电路用于独立地转换输入信号的阻抗。第一恒流源连接到设置在第一射极跟随器电路中的第一晶体管的发射极，第二恒流源连接到设置在第二射极跟随器电路中的第二晶体管的发射极。在第一射极跟随器电路中流动的恒定电流被调节为比在第二射极跟随器电路中流动的恒定电流更小的值。由于电流值的差异，第一射极跟随器电路中的第一晶体管的基极 - 发射极之间的电压与第二发射极跟随器电路中的第二晶体管的基极 - 发射极之间的电压基于上述第一和第二恒定电流。而且，上述电流差也可以在转换装置的积分电路中使用陶瓷片状电容器。

9. 发明申请

US20130215653A1 DRIVER CIRCUIT AND INVERTER CIRCUIT 有权
标题翻译：驱动电路和逆变器电路
公开(公告)号：US20130215653A1
公开(公告)日：2013-08-22
申请号：US13882531
申请日：2011-09-26
申请人： Seiichiro Kihara
发明人： Seiichiro Kihara
IPC分类号： H02H7/122 , H02H3/20
CPC分类号： H02H7/1222 , H02H3/20 , H02M1/32 , H02M1/38 , H02M7/5387 , H03K17/063 , H03K2017/066 , H03K2017/6875
摘要： The present invention provides a safe circuit that can prevent an arm short, when a half-bridge circuit is configured by using a normally-on switching element, and the half-bridge circuit is used as a driver circuit or an inverter circuit. In a driver circuit configured by a half-bridge circuit in which one of input and output terminals of a first switching element 14 is connected to a first power-supply voltage V1 on a high-voltage side, and the first switching element 14 and a second switching element 15 are connected in series, a normally-off third switching element 16 is inserted between the second switching element 15 and a second power-supply voltage V2 on a low voltage side. The third switching element 16 is turned off, when an operating voltage VH or VL supplied from control-circuit power supplies 13a and 13b is insufficient for the operation of a control circuit 11.
摘要翻译：本发明提供了一种安全电路，其可以通过使用常开开关元件来配置半桥电路，并且半桥电路用作驱动电路或逆变器电路，从而可以防止臂短路。在由半桥电路构成的驱动电路中，第一开关元件14的输入端和输出端之一与高电压侧的第一电源电压V1连接，第一开关元件14和第二开关元件15串联连接，在第二开关元件15和低压侧的第二电源电压V2之间插入常关的第三开关元件16。当从控制电路电源13a和13b提供的工作电压VH或VL对于控制电路11的操作不足时，第三开关元件16断开。

10. 发明申请

US20050210305A1 Data processor for controlling voltage supplied for processing 审中-公开
标题翻译：用于控制供应处理电压的数据处理器
公开(公告)号：US20050210305A1
公开(公告)日：2005-09-22
申请号：US11084108
申请日：2005-03-21
申请人： Seiichiro Kihara
发明人： Seiichiro Kihara
IPC分类号： G06F15/82 , G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： In a data processor, each logic circuit receives data provided from the transfer control unit being connected, processes the data, and outputs the data to the transfer control unit in the next stage. The data processing speed is changed in accordance with the level of a voltage supplied to the logic circuit. Each transfer control unit includes a plurality of C elements receiving a request pulse for data transfer provided from the preceding stage and transferring the same to the next stage, a plurality of pipeline registers, and a plurality of P circuits. Each pipeline register, in response to every reception of the request pulse, receives, holds and outputs the data requested to be transferred. Each P circuit determines frequency of data supply to the logic circuit being connected, and controls the level of a voltage supplied to the logic circuit in accordance with the determined frequency.
摘要翻译：在数据处理器中，每个逻辑电路接收从连接的传送控制单元提供的数据，处理数据，并在下一阶段将数据输出到传送控制单元。数据处理速度根据提供给逻辑电路的电压的电平而改变。每个传送控制单元包括多个C元件，其接收从前一级提供的数据传送请求脉冲并将其传送到下一级，多个流水线寄存器和多个P电路。每个流水线寄存器响应于每次接收到请求脉冲，接收，保存并输出请求传送的数据。每个P电路确定被连接的逻辑电路的数据供给频率，并且根据确定的频率来控制提供给逻辑电路的电压的电平。

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