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1. 发明申请

US20090217871A1 THIN FILM DEPOSITION APPARATUS AND METHOD OF MAINTAINING THE SAME 有权
标题翻译：薄膜沉积装置及其保持方法
公开(公告)号：US20090217871A1
公开(公告)日：2009-09-03
申请号：US12393377
申请日：2009-02-26
申请人： Se Yong Kim , Woo Chan Kim , Dong Rak Jung
发明人： Se Yong Kim , Woo Chan Kim , Dong Rak Jung
IPC分类号： B05C11/00 , C23C16/54 , G01B11/26
CPC分类号： C23C14/22 , C23C16/44
摘要： A thin film deposition apparatus and a method of maintaining the same are disclosed. In one embodiment, a thin film deposition apparatus includes: a chamber including a removable chamber cover; one or more reactors housed in the chamber; a chamber cover lifting device connected to the chamber cover. The chamber cover lifting device is configured to move the chamber cover vertically between a lower position and an upper position. The apparatus further includes a level sensing device configured to detect whether the chamber cover is level, and a level maintaining device configured to adjust the chamber cover if the chamber cover is not level. This configuration maintains the chamber cover to be level as a condition for further vertical movement of the chamber cover.
摘要翻译：公开了一种薄膜沉积装置及其保持方法。在一个实施例中，薄膜沉积设备包括：包括可拆卸室盖的室; 容纳在室中的一个或多个反应器; 连接到室盖的室盖提升装置。室盖提升装置构造成在下位置和上位置之间垂直移动室盖。该装置还包括液位感测装置，其被配置为检测腔室盖是否水平;以及水平维持装置，其被配置为如果腔室盖不平坦则调节腔室盖。这种构造保持室盖被平坦化，作为室盖的进一步垂直移动的条件。

2. 发明授权

US06275204B1 Circuit for driving address electrodes of a plasma display panel system 有权
标题翻译：用于驱动等离子体显示面板系统的寻址电极的电路
公开(公告)号：US06275204B1
公开(公告)日：2001-08-14
申请号：US09241398
申请日：1999-02-02
申请人： Se-Yong Kim
发明人： Se-Yong Kim
IPC分类号： G09G328
CPC分类号： G09G5/006 , G09G3/2003 , G09G3/288 , G09G2310/0281 , G09G2310/0297 , H04N5/70 , H04N9/30
摘要： A circuit for driving address electrodes of a plasma display panel system is disclosed. A data interfacing section outputs red, green and blue data arranged on 12 columns×107 rows to an address electrode driving IC. The address electrode driving IC has 4 input pins for receiving 4 bits of the red, green and blue data from the data interfacing section over 18 times and 72 output pins for outputting the received red, green and blue data. Accordingly, each of the address electrode driving ICs processes the red, green and blue data corresponding to a multiple of 12. That is, the red, green and blue data arranged on an identical row of the interfacing section having the red, green and blue data arranged in 12 columns×107 rows are inputted in an identical address electrode driving IC. Accordingly, the data interfacing section can execute an operation for outputting the red, green and blue data although all of 1280 units of the red, green and blue data are not inputted. Consequently, a storage capacity of the data interfacing section can be reduced and a cost of production of the flat panel display apparatus can be reduced.
摘要翻译：公开了一种用于驱动等离子体显示面板系统的寻址电极的电路。数据接口部分将布置在12列×107行的红色，绿色和蓝色数据输出到寻址电极驱动IC。地址电极驱动IC具有4个输入引脚，用于接收来自数据接口部分的红，绿和蓝数据的4位超过18次，72个输出引脚用于输出接收到的红，绿和蓝数据。因此，每个寻址电极驱动IC处理对应于12的倍数的红，绿和蓝数据。也就是说，布置在具有红色，绿色和蓝色的接口部分的相同行上的红色，绿色和蓝色数据排列成12列×107行的数据被输入到相同的地址电极驱动IC中。因此，数据接口部分可以执行用于输出红色，绿色和蓝色数据的操作，尽管红色，绿色和蓝色数据的1280个单元都不被输入。因此，能够减少数据接口部的存储容量，能够降低平板显示装置的制造成本。

3. 发明授权

US6081303A Method and apparatus for controlling a timing of an alternating current plasma display flat panel system 失效
标题翻译：用于控制交流等离子体显示器平板系统的定时的方法和装置
公开(公告)号：US6081303A
公开(公告)日：2000-06-27
申请号：US79203
申请日：1998-05-15
申请人： Se-Yong Kim
发明人： Se-Yong Kim
IPC分类号： H04N5/66 , G09G3/296 , G09G5/18 , H04N5/05 , H04N5/06
CPC分类号： G09G3/296 , G09G5/18 , G09G2330/06
摘要： A method and an apparatus for control a timing in a flat panel display system are disclosed. In an alternating current plasma display system for respectively driving a plurality of subfields at every field in three steps such as a) entering and for eliminating a whole pixel for a first predetermined time, b) entering data for a second predetermined time and c) maintaining a discharge at every subfield for times which are different from one another, a first clock generator generates a first clock signal having a high frequency. A second clock generator generates a second clock signal having a low frequency. A first counter counts the second clock signal in response to a vertical synchronizing signal, and generates both a first pulse signal which sets the first and second predetermined times respectively in steps a) and b) in the respective subfield sections and a second pulse signal which sets times in step c) in the respective subfield sections which are different from one another. A second counter counts the second clock signal to detect time intervals of sections in steps a) and b) in response to the first pulse signal. A third counter counts the second clock signal in response to the second pulse signal to detect times in steps c) which are different from one another. A first control signal generator inputs outputs of the second and the third counters and the second clock signal, and generates timing control signals to drive a scan electrode, a maintenance electrode and an address electrode. A second control signal generator inputs both an output of the second counter and the first clock signal, and generates timing control signals to enter data. Consequently, a simplification of the design of the timing control apparatus and the decrease of a noise contribute to a cost reduction along with a reliability of the products.
摘要翻译：公开了一种用于控制平板显示系统中的定时的方法和装置。在交流电等离子体显示系统中，用于在三个步骤中分别驱动每个场的多个子场，例如a）进入并消除整个像素达到第一预定时间，b）在第二预定时间内输入数据，以及c）保持在每个子场的放电时间彼此不同，第一时钟发生器产生具有高频率的第一时钟信号。第二时钟发生器产生具有低频率的第二时钟信号。第一计数器响应于垂直同步信号对第二时钟信号进行计数，并且在各个子场部分中的步骤a）和b）中分别产生设置第一和第二预定时间的第一脉冲信号和第二脉冲信号，第二脉冲信号在步骤c）中设置彼此不同的各个子区段中的时间。第二计数器对第二时钟信号进行计数，以响应于第一脉冲信号在步骤a）和b）中检测部分的时间间隔。第三计数器响应于第二脉冲信号对第二时钟信号进行计数，以检测彼此不同的步骤c）中的时间。第一控制信号发生器输入第二和第三计数器的输出和第二时钟信号，并产生用于驱动扫描电极，维护电极和寻址电极的定时控制信号。第二控制信号发生器输入第二计数器的输出和第一时钟信号，并产生定时控制信号以输入数据。因此，简化时序控制装置的设计和降低噪声有助于成本降低以及产品的可靠性。

4. 发明申请

US20120105424A1 DISPLAY MODULE AND DISPLAY SYSTEM 有权
标题翻译：显示模块和显示系统
公开(公告)号：US20120105424A1
公开(公告)日：2012-05-03
申请号：US13278504
申请日：2011-10-21
申请人： Joo-yeon LEE , Sang Chul LEE , Jong Seo LEE , Se Yong KIM
发明人： Joo-yeon LEE , Sang Chul LEE , Jong Seo LEE , Se Yong KIM
IPC分类号： G09G5/00
CPC分类号： G06F3/041 , A47F3/001 , A47F3/0404 , A47F3/043 , A47F3/0434 , A47F11/06 , G02F2001/133388 , G06F1/1626 , G06F1/1637 , G06F1/1647 , G07F9/023 , G07F9/105 , G07F11/00 , G09F9/35 , G09F13/0413 , G09F13/12 , G09F23/0058 , G09F23/04 , G09F23/065 , G09F27/00 , G09F2023/0033 , G09F2027/001 , G09G2380/06 , G09G2380/16
摘要： Disclosed is a display module including a transparent display panel and a frame to fix a side of the transparent display panel, wherein the frame has a communication unit to receive data from the outside, a controller to process the received data and to output a drive command corresponding to the processed data and a display drive unit to drive the transparent display panel in response to the drive command from the controller. A display system includes a system body and a display module detachably mounted in the system body.
摘要翻译：公开了一种显示模块，包括透明显示面板和用于固定透明显示面板侧面的框架，其中框架具有用于从外部接收数据的通信单元，控制器，用于处理接收到的数据并输出驱动命令对应于所处理的数据;以及显示驱动单元，用于响应于来自控制器的驱动命令来驱动透明显示面板。显示系统包括系统主体和可拆卸地安装在系统主体中的显示模块。

5. 发明授权

US06211867B1 Method and apparatus for controlling switching timing of power recovery circuit in AC type plasma display panel system 有权
标题翻译：用于控制AC型等离子体显示面板系统中功率恢复电路的开关时序的方法和装置
公开(公告)号：US06211867B1
公开(公告)日：2001-04-03
申请号：US09243447
申请日：1999-02-03
申请人： Se-Yong Kim
发明人： Se-Yong Kim
IPC分类号： G09G500
CPC分类号： H04N5/70 , G09G3/2022 , G09G3/294 , G09G3/2965 , G09G2310/066 , H04N5/63
摘要： A method and an apparatus for variably controlling a switching timing of a power recovery circuit of a plasma display panel television is disclosed. A variableness range pulse generating section generates a variableness range pulse which determines a maximum variableness range of a recovered power applying time. A first counter counts a clock signal in response to the variableness range pulse and periodically outputs a counted value. Second and third counters count a switching time of first and second switches, respectively, and sets first and second reference values. A rising pulse generating section periodically compares the counted value with the first reference value and converts a logic level of an output signal from low to high when the counted value is identical with the first reference value. A falling pulse generating section periodically compares the counted value with the second reference value and converts a logic level of an output signal from high to low. An AND-gate logically multiplies an output of the rising pulse generating section and an output of the falling pulse generating section to generate a control signal. A pulse sustentation period of the control signal is determined by the first and second reference values which can be variably determined from an outside.
摘要翻译：公开了一种用于可变地控制等离子体显示面板电视的功率恢复电路的切换定时的方法和装置。可变范围脉冲发生部分生成确定恢复的电力施加时间的最大可变范围的可变范围脉冲。第一计数器响应于可变范围脉冲对时钟信号进行计数，并周期性地输出计数值。第二和第三计数器分别计数第一和第二开关的切换时间，并设置第一和第二参考值。当计数值与第一参考值相同时，上升脉冲发生部分周期性地将计数值与第一参考值进行比较，并将输出信号的逻辑电平从低变为高。下降脉冲发生部分将计数值与第二参考值周期性地进行比较，并将输出信号的逻辑电平从高变为低。与门逻辑地将上升脉冲发生部分的输出和下降脉冲发生部分的输出相乘以产生控制信号。控制信号的脉冲持续时间由可从外部可变地确定的第一和第二参考值确定。

6. 发明授权

US09311834B2 Display module including transparent display panel and display system including the display module 有权
标题翻译：显示模块包括透明显示面板和显示系统，包括显示模块
公开(公告)号：US09311834B2
公开(公告)日：2016-04-12
申请号：US13278504
申请日：2011-10-21
申请人： Joo-yeon Lee , Sang Chul Lee , Jong Seo Lee , Se Yong Kim
发明人： Joo-yeon Lee , Sang Chul Lee , Jong Seo Lee , Se Yong Kim
IPC分类号： G09F9/35 , A47F3/00 , G07F9/02 , G06F1/16 , G07F11/00 , G07F9/10 , A47F3/04 , G09F23/00 , G09F13/04 , G09F13/12 , G02F1/1333 , G09F27/00
CPC分类号： G06F3/041 , A47F3/001 , A47F3/0404 , A47F3/043 , A47F3/0434 , A47F11/06 , G02F2001/133388 , G06F1/1626 , G06F1/1637 , G06F1/1647 , G07F9/023 , G07F9/105 , G07F11/00 , G09F9/35 , G09F13/0413 , G09F13/12 , G09F23/0058 , G09F23/04 , G09F23/065 , G09F27/00 , G09F2023/0033 , G09F2027/001 , G09G2380/06 , G09G2380/16
摘要： Disclosed is a display module including a transparent display panel and a frame to fix a side of the transparent display panel, wherein the frame has a communication unit to receive data from the outside, a controller to process the received data and to output a drive command corresponding to the processed data and a display drive unit to drive the transparent display panel in response to the drive command from the controller. A display system includes a system body and a display module detachably mounted in the system body.
摘要翻译：公开了一种显示模块，包括透明显示面板和用于固定透明显示面板侧面的框架，其中框架具有用于从外部接收数据的通信单元，控制器，用于处理接收到的数据并输出驱动命令对应于所处理的数据;以及显示驱动单元，用于响应于来自控制器的驱动命令来驱动透明显示面板。显示系统包括系统主体和可拆卸地安装在系统主体中的显示模块。

7. 发明授权

US06195071B1 Timing control circuit of AC type plasma display panel system 有权
标题翻译：交流型等离子显示屏系统定时控制电路
公开(公告)号：US06195071B1
公开(公告)日：2001-02-27
申请号：US09243448
申请日：1999-02-03
申请人： Se-Yong Kim
发明人： Se-Yong Kim
IPC分类号： G09G328
CPC分类号： H04N9/30 , G09G3/296 , G09G5/18 , G09G5/395 , H04N5/70
摘要： Disclosed is a timing circuit which produces control signals by which a data interfacing section can simultaneously implement input and output operations of a video data from a frame memory to an address electrode driving section, respectively. A first pulse signal whose pulse duration corresponds to a whole horizontal line time, a second pulse signal which is identical to a delayed first pulse signal by one horizontal line time and a third pulse signal whose pulse duration is one horizontal line time longer than that of the first pulse signal are produced by using a system clock signal of a 2 MHz frequency. During the pulse duration of the first and second pulse signals, first and second clock signals which contains 480 numbers of clock pulses with a period of one horizontal line time are produced by counting another system clock signal of a 25 MHz frequency. During the pulse duration of the third pulse signal, a third clock signal which contains 481 numbers of clock pulses with the period of one horizontal line time is produced by counting the system clock signal of the 25 MHz frequency. The first, second and third clock signals are provided to the frame memory, the address electrode driving section and the data interfacing section, respectively. By means of operations of these three clock signals, the data interfacing section can simultaneously implement the input operation of the video data of one horizontal line from the frame memory and the output operation of the video data to the address electrode driving section.
摘要翻译：公开了一种定时电路，其产生控制信号，通过该控制信号，数据接口部分可以分别同时实现从帧存储器到地址电极驱动部分的视频数据的输入和输出操作。第一脉冲信号，其脉冲持续时间对应于整个水平行时间，第二脉冲信号与延迟的第一脉冲信号相同一个水平行时间，第三脉冲信号的脉冲持续时间比一个水平行时间长通过使用2MHz频率的系统时钟信号来产生第一脉冲信号。在第一和第二脉冲信号的脉冲持续时间期间，通过对25MHz频率的另一个系统时钟信号进行计数，产生包含480个时钟脉冲的第一和第二时钟信号，其中周期为一个水平行时间。在第三脉冲信号的脉冲持续时间期间，通过对25MHz频率的系统时钟信号进行计数，产生包含481个具有一个水平行时间周期的时钟脉冲数的第三时钟信号。第一，第二和第三时钟信号分别提供给帧存储器，寻址电极驱动部分和数据接口部分。通过这三个时钟信号的操作，数据接口部分可以同时实现来自帧存储器的一条水平行的视频数据的输入操作和视频数据的输出操作到寻址电极驱动部分。

8. 发明授权

US06191762B1 Timing control circuit of AC type plasma display panel system 有权
标题翻译：交流型等离子显示屏系统定时控制电路
公开(公告)号：US06191762B1
公开(公告)日：2001-02-20
申请号：US09241408
申请日：1999-02-02
申请人： Se-Yong Kim
发明人： Se-Yong Kim
IPC分类号： G09G328
CPC分类号： G09G5/18 , G09G3/296
摘要： Disclosed is a timing circuit which produces control signals by which a data interfacing section can simultaneously implement input and output operations of a video data from a frame memory and to an address electrode driving section, respectively. A first pulse signal whose pulse duration corresponds to a whole horizontal line time, a second pulse signal which is identical to a delayed first pulse signal by one horizontal line time and a third pulse signal whose pulse duration is the one horizontal line time longer than that of the first pulse signal are produced by using a system clock signal of 2 MHz. During the pulse duration of the third pulse signal, a first clock signal which contains pulse signals whose numbers are one number larger than the numbers of whole horizontal lines (480) by using a system clock signal of 25 MHz. The first clock signal is provided to the data interfacing section to control the input and output operations thereof. A clock signal including 480 numbers of pulses obtained from a logical multiplication of the first clock signal and the first pulse signal is used for a control of an output operation of the frame memory. Another clock signal, which is delayed by the one horizontal line time, including 480 numbers of pulses obtained from a logical multiplication of the first clock signal and the second pulse signal is used for a control of an input operation of the address electrode driving section.
摘要翻译：公开了一种定时电路，其产生控制信号，通过该控制信号，数据接口部分可以分别同时实现来自帧存储器和寻址电极驱动部分的视频数据的输入和输出操作。第一脉冲信号，其脉冲持续时间对应于整个水平行时间，第二脉冲信号与延迟的第一脉冲信号相同一个水平行时间;以及第三脉冲信号，其脉冲持续时间比一个水平行时间长的第一脉冲信号通过使用2MHz的系统时钟信号产生。在第三脉冲信号的脉冲持续时间期间，通过使用25MHz的系统时钟信号，包含数字大于全部水平线数（480）的数字的脉冲信号的第一时钟信号。第一时钟信号被提供给数据接口部分以控制其输入和输出操作。包括从第一时钟信号和第一脉冲信号的逻辑乘法获得的480个脉冲数的时钟信号用于对帧存储器的输出操作的控制。使用延迟了一个水平行时间的另一个时钟信号，包括从第一时钟信号和第二脉冲信号的逻辑乘法获得的480个脉冲数，用于控制地址电极驱动部分的输入操作。

9. 发明授权

US09371583B2 Plasma processing member, deposition apparatus including the same, and depositing method using the same 有权
标题翻译：等离子体处理构件，包括该等离子体处理构件的沉积装置以及使用其的沉积方法
公开(公告)号：US09371583B2
公开(公告)日：2016-06-21
申请号：US12577885
申请日：2009-10-13
申请人： Ki Jong Kim , Hyun Kyu Cho , Jin Su Lee , Se Yong Kim
发明人： Ki Jong Kim , Hyun Kyu Cho , Jin Su Lee , Se Yong Kim
IPC分类号： C23C16/00 , C23C16/455 , C23C16/509 , H01J37/32
CPC分类号： C23C16/45542 , C23C16/45551 , C23C16/5096 , H01J37/32009 , H01J37/32091 , H01J37/32146 , H01J37/3244 , H01J37/32568 , H01J37/32733 , H01J2237/332
摘要： A deposition apparatus according to an exemplary embodiment of the present invention includes a plurality of reaction spaces, a plurality of plasma electrodes respectively disposed in the reaction spaces, a first plasma processor connected to at least two plasma electrodes, and a first plasma power source connected to the first plasma processor. The first plasma processor may include a plasma distributor or a plasma splitter.
摘要翻译：根据本发明的示例性实施例的沉积设备包括多个反应空间，分别设置在反应空间中的多个等离子体电极，连接到至少两个等离子体电极的第一等离子体处理器和连接到第一等离子体电源的第一等离子体电源到第一等离子体处理器。第一等离子体处理器可以包括等离子体分配器或等离子体分离器。

10. 发明授权

US06333725B1 Data interfacing apparatus of AC type plasma display panel system 有权
标题翻译：交流式等离子显示面板系统的数据接口装置
公开(公告)号：US06333725B1
公开(公告)日：2001-12-25
申请号：US09241397
申请日：1999-02-02
申请人： Se-Yong Kim
发明人： Se-Yong Kim
IPC分类号： G09G328
CPC分类号： G09G5/006 , G09G3/2085 , G09G3/288 , G09G5/18 , G09G5/395
摘要： A data interfacing apparatus for interfacing a frame memory with upper and lower address electrode drivers in an alternating current type plasma display panel system is disclosed. The data interfacing apparatus includes a pair of provisional storing sections for provisionally storing RGB data supplied from the frame memory and a shift signal generator for generating a clock signal to provide the clock signal to the respective provisional storing sections. Each of the provisional storing sections includes N shift registers consisting of M delayed flip-flops. Respective input terminals of the shift registers are connected to N output terminals of the frame memory one-to-one. The respective shift registers shift M times the RGB data, which is transferred to the respective input terminals by one bit from the frame memory, and provisionally latch N×M bits RGB data in response to a clock signal. The shift signal generator produces M shift signals by using a first signal which represents a start of a horizontal line and a second signal which is a system reference clock, and then produces the clock signal by using a third signal whose logical level is alternately inverted by the period of the horizontal line and the M shift signals.
摘要翻译：公开了一种用于在交流型等离子体显示面板系统中将帧存储器与上下寻址电极驱动器接口的数据接口装置。数据接口装置包括用于临时存储从帧存储器提供的RGB数据的一对临时存储部分和用于产生时钟信号的移位信号发生器，以向相应的临时存储部分提供时钟信号。每个临时存储部分包括由M个延迟的触发器组成的N个移位寄存器。移位寄存器的各个输入端子一一对应地连接到帧存储器的N个输出端子。相应的移位寄存器将RGB数据移位到RGB数据，RGB数据从帧存储器传送到相应的输入端子一位，并且响应于时钟信号临时锁存N×M位RGB数据。移位信号发生器通过使用表示水平线的开始的第一信号和作为系统参考时钟的第二信号产生M个移位信号，然后通过使用逻辑电平被逻辑电平交替地反相的第三信号产生时钟信号水平线和M移位信号的周期。

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