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1. 发明授权

US06704846B1 Dynamic memory arbitration in an MPEG-2 decoding System 失效
标题翻译： MPEG-2解码系统中的动态内存仲裁
公开(公告)号：US06704846B1
公开(公告)日：2004-03-09
申请号：US09105492
申请日：1998-06-26
申请人： Scarlett Z. Wu , Darren D. Neuman , Arvind B. Patwardhan
发明人： Scarlett Z. Wu , Darren D. Neuman , Arvind B. Patwardhan
IPC分类号： G06F1200
CPC分类号： G06F9/3879 , H04N19/423 , H04N19/43 , H04N19/44
摘要： A video decoding system includes an embedded microcontroller that provides memory arbitration in addition to processing and control functions. The microcontroller architecture provides a first-in, first-out (FIFO) queue for storing memory access instructions and a processing logic for executing software instructions. The microcontroller processing logic determines which components within the decoding system need access to memory and stores a sequence of memory access instructions into the FIFO queue. Each memory access instruction is associated with one decoder component. When main memory becomes available, a memory access instruction is dequeued from the FIFO and transmitted to the associated decoder component, which is then permitted to access memory. The microcontroller receives indicator signals from the decoder components that indicate when the decoder components have finished accessing memory and, thus, when the memory device is available for subsequent transactions.
摘要翻译：视频解码系统包括除了处理和控制功能之外提供存储器仲裁的嵌入式微控制器。微控制器架构提供了用于存储存储器访问指令的先进先出（FIFO）队列和用于执行软件指令的处理逻辑。微控制器处理逻辑确定解码系统中的哪些组件需要访问存储器并将一系列存储器访问指令存储到FIFO队列中。每个存储器访问指令与一个解码器组件相关联。当主存储器变为可用时，存储器访问指令从FIFO出来并发送到相关联的解码器组件，然后允许其访问存储器。微控制器接收来自解码器组件的指示符信号，其指示解码器组件何时完成访问存储器，并且因此当存储器设备可用于后续事务时。

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